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  ON Semiconductor Electronic Components Datasheet  

MC74ACT377 Datasheet

Octal D Flip-Flop

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MC74AC377, MC74ACT377
Octal D Flip-Flop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
Ideal for Addressable Register Applications
Clock Enable for Address and Data Synchronization Applications
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Outputs Source/Sink 24 mA
See MC74AC273 for Master Reset Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
ACT377 Has TTL Compatible Inputs
MSL = 1 for all Surface Mount
Chip Complexity: 292 FETs or 73 Gates
These are Pb−Free Devices
www.onsemi.com
SOIC−20W
DW SUFFIX
CASE 751D
1
TSSOP−20
DT SUFFIX
CASE 948E
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
CE O0 D0 D1 O1 O2 D2 D3 O3 GND
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
PIN NAMES
PIN
D0−D7
CE
Q0−Q7
CP
FUNCTION
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 10
1
D0 D1 D2 D3 D4 D5 D6 D7
CP
CE
O0 O1 O2 O3 O4 O5 O6 O7
Figure 2. Logic Symbol
Publication Order Number:
MC74AC377/D


  ON Semiconductor Electronic Components Datasheet  

MC74ACT377 Datasheet

Octal D Flip-Flop

No Preview Available !

MC74AC377, MC74ACT377
MODE SELECT-FUNCTION TABLE
Operating Mode
Load 1
Load 0
CP
Hold (Do Nothing)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
X
Inputs
CE
L
L
H
H
Dn
H
L
X
X
Outputs
Qn
H
L
No Change
No Change
D0 D1 D2 D3 D4 D5 D6 D7
CE
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
CP
O0 O1 O2 O3 O4 O5 O6 O7
Please note that this diagram is provided only for the understanding of
logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
www.onsemi.com
2


Part Number MC74ACT377
Description Octal D Flip-Flop
Maker ON Semiconductor
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MC74ACT377 Datasheet PDF






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