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  ON Semiconductor Electronic Components Datasheet  

NB100ELT23L Datasheet

Dual Differential LVPECL/LVDS to LVTTL Translator

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NB100ELT23L pdf
NB100ELT23L
3.3V Dual Differential
LVPECL/LVDS to LVTTL
Translator
The NB100ELT23L is a dual differential LVPECL/LVDS to LVTTL
translator. Because LVPECL (Positive ECL) or LVDS levels are used,
only +3.3 V and ground are required. The small outline 8-lead package
and the dual gate design of the ELT23L makes it ideal for applications
which require the translation of a clock and a data signal.
The ELT23L is available in only the ECL 100K standard. Since
there are no LVPECL outputs or an external VBB reference, the
ELT23L does not require both ECL standard versions. The LVPECL
inputs are differential. Therefore, the NB100ELT23L can accept any
standard differential LVPECL/LVDS input referenced from a VCC of
+3.3 V.
Features
2.1 ns Typical Propagation Delay
Maximum Operating Frequency > 160 MHz
24 mA LVTTL Outputs
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
www.onsemi.com
8
1
MARKING
DIAGRAMS*
SOIC−8
D SUFFIX
CASE 751
8
KT23L
ALYW
G
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
K23L
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 12
1
Publication Order Number:
NB100ELT23L/D


  ON Semiconductor Electronic Components Datasheet  

NB100ELT23L Datasheet

Dual Differential LVPECL/LVDS to LVTTL Translator

No Preview Available !

NB100ELT23L pdf
NB100ELT23L
D0 1
8 VCC
D0 2
D1 3
LVPECL LVTTL
7 Q0
6 Q1
D1 4
5 GND
Figure 1. 8−Lead Pinout (Top View) and
Logic Diagram
Table 1. PIN DESCRIPTION
PIN FUNCTION
Q0, Q1
LVTTL Outputs
D0*, D1*
D0**, D1**
Differential LVPECL Inputs
VCC
GND
Positive Supply
Ground
*Pins will default to VCC/2 when left open. If connected to a
common termination voltage under no signal conditions, then the
device will be susceptible to self−oscillation.
**Pins will default to 2/3 VCC when left open. If connected to a
common termination voltage under no signal conditions, then the
device will be susceptible to self−oscillation. See AND8020,
Section 6 for options.
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
D
D
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SO−8
TSSOP−8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
50 kW
75 kW
50 kW
> 1.5 kV
> 100 V
> 2 kV
Pb−Free Pkg
Level 1
Level 3
UL 94 V−0 @ 1.25 in
91 Devices
www.onsemi.com
2


Part Number NB100ELT23L
Description Dual Differential LVPECL/LVDS to LVTTL Translator
Maker ON Semiconductor
Total Page 7 Pages
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