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  ON Semiconductor Electronic Components Datasheet  

NB100LVEP221 Datasheet

1:20 Differential HSTL/ECL/PECL Clock Driver

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NB100LVEP221
2.5V/3.3V 1:20 Differential
HSTL/ECL/PECL Clock Driver
Description
The NB100LVEP221 is a low skew 1to20 differential clock
driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The two clock inputs are differential
ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The
LVPECL input signals can be either differential configuration or
singleended (if the VBB output is used).
The LVEP221 specifically guarantees low outputtooutput skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
To ensure tightest skew, both sides of differential outputs should be
terminated identically into 50 W even if only one output is being used.
If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The NB100LVEP221, as with most other ECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows the
LVEP221 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power
supplies. For more information on PECL terminations, designers should
refer to Application Note AND8020/D.
The VBB pin, an internally generated voltage supply, is awvwaw.iDlaatabSlheeett4oU.ctohmis
device only. For singleended LVPECL input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.
Singleended CLK input operation is limited to a VCC 3.0 V in
LVPECL mode, or VEE 3.0 V in NECL mode.
Features
15 ps Typical OutputtoOutput Skew
40 ps Typical DevicetoDevice Skew
Jitter Less than 2 ps RMS
Maximum Frequency > 1.0 GHz Typical
Thermally Enhanced 52Lead LQFP
VBB Output
540 ps Typical Propagation Delay
LVPECL and HSTL Mode Operating Range:
VCC = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 2.375 V to 3.8 V
Q Output will Default Low with Inputs Open or at VEE
Pin Compatible with Motorola MC100EP221
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 7
1
http://onsemi.com
MARKING
DIAGRAM*
LQFP52
FA SUFFIX
CASE 848H
NB100
LVEP221
AWLYYWWG
52
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Publication Order Number:
NB100LVEP221/D


  ON Semiconductor Electronic Components Datasheet  

NB100LVEP221 Datasheet

1:20 Differential HSTL/ECL/PECL Clock Driver

No Preview Available !

NB100LVEP221
VCC0
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
39 38 37 36 35 34 33 32 31 30 29 28 27
40 26
41 25
42 24
43 23
44 22
45 21
46
NB100LVEP221
20
47 19
48 18
49 17
50 16
51 15
52 14
1 2 3 4 5 6 7 8 9 10 11 12 13
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
Q16
Q16
Q17
Q17
VCC0
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally
conductive exposed pad on package bottom (see package case drawing) must be attached to a heatsinking conduit, capable of transfer-
ring 1.2 Watts. This exposed pad is electrically connected to VEE internally.
Table 1. PIN DESCRIPTION
Figure 1. 52Lead LQFP Pinout (Top View)
PIN FUNCTION
CLK0*, CLK0**
CLK1*, CLK1**
ECL/PECL Differential Inputs
ECL/PECL or HSTL Differential Inputs
Q0:19, Q0:19 ECL/PECL Differential Outputs
CLK_SEL*
VBB
ECL/PECL Active Clock Select Input
Reference Voltage Output
VCC/VCCO
Positive Supply
VEE***
Negative Supply
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the
package is electrically connected to VEE internally.
Table 2. FUNCTION TABLE
CLK_SEL
Active Input
CLK0
CLK0
CLK1
CLK1
CLK_SEL
0
20
Q0 Q19
Q0 Q19
20
1
VBB
VCC
VEE
L CLK0, CLK0
H CLK1, CLK1
Figure 2. Logic Diagram
http://onsemi.com
2


Part Number NB100LVEP221
Description 1:20 Differential HSTL/ECL/PECL Clock Driver
Maker ON Semiconductor
Total Page 11 Pages
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