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NB100LVEP221 - 1:20 Differential HSTL/ECL/PECL Clock Driver

Description

designed with clock distribution in mind, accepting two clock sources into an input multiplexer.

The two clock inputs are differential ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels.

Features

  • 15 ps Typical Output.
  • to.
  • Output Skew.
  • 40 ps Typical Device.
  • to.
  • Device Skew.
  • Jitter Less than 2 ps RMS.
  • Maximum Frequency > 1.0 GHz Typical.
  • Thermally Enhanced 52.
  • Lead QFN Package.
  • VBB Output.
  • 540 ps Typical Propagation Delay.
  • LVPECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V.
  • NECL Mode Operating Range: VCC = 0 V with VEE =.
  • 2.375 V to.

📥 Download Datasheet

Datasheet Details

Part number NB100LVEP221
Manufacturer onsemi
File Size 130.60 KB
Description 1:20 Differential HSTL/ECL/PECL Clock Driver
Datasheet download datasheet NB100LVEP221 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NB100LVEP221 2.5V/3.3V 2:1:20 Differential HSTL/ECL/PECL Clock Driver Description The NB100LVEP221 is a low skew 2:1:20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The LVPECL input signals can be either differential configuration or single−ended (if the VBB output is used). The LVEP221 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure tightest skew, both sides of differential outputs should be terminated identically into 50 W even if only one output is being used.
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