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  ON Semiconductor Electronic Components Datasheet  

NB100LVEP224 Datasheet

1:24 Differential ECL/PECL Clock Driver

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NB100LVEP224 pdf
NB100LVEP224
2.5V/3.3V 1:24 Differential
ECL/PECL Clock Driver with
Clock Select and Output
Enable
Description
The NB100LVEP224 is a low skew 1to24 differential clock
driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The part is designed for use in low
voltage applications which require a large number of outputs to drive
precisely aligned low skew signals to their destination. The two clock
inputs are differential ECL/PECL and they are selected by the
CLK_SEL pin. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE) is synchronous
ensuring the outputs will only be enabled/disabled when they are
already in LOW state (See Figure 4).
The NB100LVEP224 guarantees low outputtooutput skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to “reduce power and switching noise as much as
possible.” Any unused single line of a differential pair should be
terminated the same as the used line to maintain balancewdwwl.DoaatadShseeot4nU.ctohme
differential driver outputs. The wide VIHCMR specification allows
both pair of CLOCK inputs to accept LVDS levels.
The NB100LVEP224, as with most other ECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP224 to be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Singleended CLK input operation is
limited to a VCC 3.0 V in LVPECL mode, or VEE 3.0 V in NECL
mode. In a PECL environment, series or Thevenin line terminations
are typically used as they require no additional power supplies. For
more information on PECL terminations, designers should refer to
Application Note AND8020/D.
http://onsemi.com
MARKING
DIAGRAM*
LQFP64
FA SUFFIX
CASE 848G
NB100
LVEP224
AWLYYWWG
64
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Features
20 ps Typical OutputtoOutput Skew
75 ps Typical DevicetoDevice Skew
Maximum Frequency > 1 GHz
650 ps Typical Propagation Delay
LVPECL Mode Operating Range:
VCC = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 2.375 V to 3.8 V
Internal Input Pulldown Resistors
Q Output will Default Low with Inputs Open or at VEE
Thermally Enhanced 64Lead LQFP
CLOCK Inputs are LVDSCompatible; Requires
External 100 W LVDS Termination Resistor
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 7
1
Publication Order Number:
NB100LVEP224/D


  ON Semiconductor Electronic Components Datasheet  

NB100LVEP224 Datasheet

1:24 Differential ECL/PECL Clock Driver

No Preview Available !

NB100LVEP224 pdf
NB100LVEP224
VCCO
Q7
Q7
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
VCCO
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49 32
50 31
51 30
52 29
53 28
54 27
55 26
56 25
NB100LVEP224
57 24
58 23
59 22
60 21
61 20
62 19
63 18
64 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCCO
Q15
Q15
Q16
Q16
Q17
Q17
Q18
Q18
Q19
Q19
Q20
Q20
Q21
Q21
VCCO
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally
conductive exposed pad on package bottom (see package case drawing) must be attached to a heatsinking conduit, capable of transfer-
ring 1.2 Watts. This exposed pad is electrically connected to VEE internally.
Figure 1. 64Lead LQFP Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN FUNCTION
CLK0*, CLK0**
CLK1*, CLK1**
CLK_SEL*
OE*
Q0Q23, Q0Q23
VCC, VCCO
VEE***
ECL Differential Input Clock
ECL Differential Input Clock
ECL Input CLK Select
ECL Output Enable
ECL Differential Outputs
Positive Supply
Negative Supply
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the
package is electrically connected to VEE internally.
Table 2. FUNCTION TABLE
OE (1) CLK_SEL
Q0Q23
Q0Q23
LL
LH
HL
HH
CLK0
CLK1
L
L
CLK0
CLK1
H
H
1. The OE (Output Enable) signal is synchronized with the
falling edge of the LVPECL_CLK signal.
http://onsemi.com
2


Part Number NB100LVEP224
Description 1:24 Differential ECL/PECL Clock Driver
Maker ON Semiconductor
Total Page 10 Pages
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