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NB100LVEP91 Datasheet

2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator

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NB100LVEP91
2.5 V/3.3 V Any Level
Positive Input to
-2.5 V/-3.3 V LVNECL
Output Translator
Description
The NB100LVEP91 is a triple any level positive input to NECL
output translator. The device accepts LVPECL, LVTTL, LVCMOS,
HSTL, CML or LVDS signals, and translates them to differential
LVNECL output signals (2.5 V / 3.3 V).
To accomplish the level translation the LVEP91 requires three
power rails. The VCC pins should be connected to the positive power
supply, and the VEE pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
VEE and VCC should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D input will be biased at VCC/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
Maximum Input Clock Frequency > 2.0 GHz Typical
Maximum Input Data Rate > 2.0 Gb/s Typical
500 ps Typical Propagation Delay
Operating Range:
VCC = 2.375 V to 3.8 V; VEE = 2.375 V to 3.8 V; GND = 0 V
Q Output will Default LOW with Inputs Open or at GND
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
20
1
SOIC20 WB
DW SUFFIX
CASE 751D05
24 1
QFN24
MN SUFFIX
CASE 485L01
MARKING DIAGRAMS*
20
NB100LVEP91
AWLYYWWG
1
24
1 N100
VP91
ALYWG
G
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping
MB100LVEP91DWG
SOIC20 WB 38 Units/Tube
(Pb-Free)
MB100LVEP91DWR2G SOIC20 WB 1000/Tape & Reel
(Pb-Free)
MB100LVEP91MNG
QFN24
(Pb-Free)
92 Units/Tube
MB100LVEP91MNR2G
QFN24 3000/Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
August, 2016 Rev. 19
1
Publication Order Number:
NB100LVEP91/D


  ON Semiconductor Electronic Components Datasheet  

NB100LVEP91 Datasheet

2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator

No Preview Available !

NB100LVEP91
Positive Level
Input
D0
R1
D0
R1
R2
NECL Output
Q0
Q0
D1
R1
D1
R1
R2
Q1
Q1
D2
R1
D2
R1
R2
Q2
Q2
Figure 1. Logic Diagram
VCC
VBB
GND
VEE
Table 1. PIN DESCRIPTION
SOIC
1, 20
Pin
QFN
3, 4, 12
Name
VCC
Default
I/O State
Description
− − Positive Supply Voltage. All VCC Pins must be Externally
Connected to Power Supply to Guarantee Proper Opera-
tion.
10
15, 16
VEE
Negative Supply Voltage. All VEE Pins must be Externally
Connected to Power Supply to Guarantee Proper Opera-
tion.
14, 17
19, 20, 23,
24
GND
Ground.
4, 7
2, 5, 8
7, 11
5, 8, 13
VBB
ECL Reference Voltage Output
D[0:2] LVPECL, LVDS, LVTTL,
Low Non-inverted Differential Inputs [0:2]. Internal 75 kW to
LVCMOS, CML, HSTL Input
GND.
3, 6, 9
6, 9, 14
D[0:2]
19,16,13 2, 22, 18 Q[0:2]
18,15,12 1, 21, 17 Q[0:2]
11 10 NC
LVPECL, LVDS,
LVTTL,LVCMOS, CML,
HSTL Input
LVNECL Output
LVNECL Output
N/A EP
High
Inverted Differential Inputs [0:2]. Internal 75 kW to GND and
75 kW to VCC. When Inputs are Left Open They Default to
(VCC GND) / 2.
Non-inverted Differential Outputs [0:2]. Typically Terminated
with 50 W to VTT = VCC 2 V
Inverted Differential Outputs [0:2]. Typically Terminated with
50 W to VTT = VCC 2 V
No Connect. The NC Pin is NOT Electrically Connected to
the Die and may Safely be Connected to Any Voltage from
VEE to VCC.
Exposed Pad. (Note 1)
1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit and may
only be electrically connected to VEE (not GND).
www.onsemi.com
2


Part Number NB100LVEP91
Description 2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator
Maker ON Semiconductor
Total Page 11 Pages
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