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  ON Semiconductor Electronic Components Datasheet  

NB3L553 Datasheet

2.5V / 3.3V / 5.0V 1:4 Clock Fanout Buffer

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NB3L553
2.5 V / 3.3 V / 5.0 V
1:4 Clock Fanout Buffer
Description
The NB3L553 is a low skew 1−to 4 clock fanout buffer, designed for
clock distribution in mind. The NB3L553 specifically guarantees low
output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
Features
Input/Output Clock Frequency up to 200 MHz
Low Skew Outputs (35 ps), Typical
RMS Phase Jitter (12 kHz – 20 MHz): 29 fs (Typical)
Output goes to Three−State Mode via OE
Operating Range: VDD = 2.375 V to 5.25 V
5 V Tolerant Input Clock ICLK
Ideal for Networking Clocks
Packaged in 8−pin SOIC
Industrial Temperature Range
These are Pb−Free Devices
ICLK
Q1
Q2
Q3
Q4
OE
Figure 1. Block Diagram
www.onsemi.com
MARKING DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
8
3L553
ALYW
G
1
3L553
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
DFN8
1
MN SUFFIX
6P MG
1 CASE 506AA
G
6P = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
PINOUT DIAGRAM
VDD
Q0
Q1
GND
1
2
3
4
8
OE
7
Q3
6
Q2
5
ICLK
ORDERING INFORMATION
Device
Package
Shipping
NB3L553DG
NB3L553DR2G
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
98 Units/Rail
2500/Tape & Reel
NB3L553MNR4G DFN−8 1000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
January, 2017 − Rev. 9
1
Publication Order Number:
NB3L553/D


  ON Semiconductor Electronic Components Datasheet  

NB3L553 Datasheet

2.5V / 3.3V / 5.0V 1:4 Clock Fanout Buffer

No Preview Available !

NB3L553
Table 1. OE, OUTPUT ENABLE FUNCTION
OE Function
0 Disable
1 Enable
Table 2. PIN DESCRIPTION
Pin #
Name
Type
Description
1 VDD
Power
Positive supply voltage (2.375 V to 5.25 V)
2 Q0 (LV)CMOS/(LV)TTL Output Clock Output 0
3 Q1 (LV)CMOS/(LV)TTL Output Clock Output 1
4 GND
Power
Negative supply voltage; Connect to ground, 0 V
5 ICLK
(LV)CMOS Input
Clock Input. 5.0 V tolerant
6 Q2 (LV)CMOS/(LV)TTL Output Clock Output 2
7 Q3 (LV)CMOS/(LV)TTL Output Clock Output 3
8 OE
(LV)TTL Input
VDD for normal operation. Pin has no internal pullup or pull down resistor for open
condition default. Use from 1 to 10 kOhms external resistor to force an open con-
dition default state.
− EP Thermal Exposed Pad (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal
conduit. Electrically connect to the most negative supply (GND) or leave uncon-
nected, floating open.
www.onsemi.com
2


Part Number NB3L553
Description 2.5V / 3.3V / 5.0V 1:4 Clock Fanout Buffer
Maker ON Semiconductor
Total Page 8 Pages
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