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NB3L853141 Datasheet

2.5V/3.3V 1:5 LVPECL Fanout Buffer

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NB3L853141
2.5V/3.3V 1:5 LVPECL
Fanout Buffer
Description
The NB3L853141 is a low skew 1:5 LVPECL Clock fanout buffer
designed explicitly for low output skew applications.
The NB3L853141 features a multiplexed input which can be driven
by either a differential or single−ended input to allow for the
distribution of a lower speed clock along with the high speed system
clock.
The SEL pin will select the differential clock inputs, CLK0 &
CLK0, when LOW (or left open and pulled LOW by the internal
pull−down resistor). When SEL is HIGH, the single−ended CLK1
input is selected.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore, all associated specification limits are referenced to the
negative edge of the clock input.
Features
700 MHz Maximum Clock Output Frequency
CLK0 and CLK0 can Accept Differential LVPECL, LVDS, HCSL,
LVHSTL, SSTL, LVCMOS
CLK1 can Accept LVCMOS and LVTTL
Five Differential LVPECL Clock Outputs
1.5 ns Maximum Propagation Delay
Operating Range: VCC = 2.375 V to 3.8 V
LVCMOS Compatible Control Inputs
Selectable Differential or LVCMOS Clock Inputs
Synchronous Clock Enable
30 ps Max. Skew Between Outputs
−40°C to +85°C Ambient Operating Temperature Range
TSSOP−20 Package
These are Pb−Free Devices
Applications
Computing and Telecom
Routers, Servers and Switches
Backplanes
www.onsemi.com
MARKING
DIAGRAM
TSSOP−20
DT SUFFIX
CASE 948E
NB3L
3141
ALYW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
EN
CLK0
CLK0
+
CLK1
SEL
0
1
D
Q
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Figure 1. Simplified Logic Diagram of
NB3L853141
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 2
1
Publication Order Number:
NB3L853141/D


  ON Semiconductor Electronic Components Datasheet  

NB3L853141 Datasheet

2.5V/3.3V 1:5 LVPECL Fanout Buffer

No Preview Available !

NB3L853141
VCC EN VCC NC CLK1 CLK0 CLK0 NC SEL VEE
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4
Note: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. Pinout (Top View) and Logic Diagram
Table 1. FUNCTION TABLE
CLK0
CLK1
SEL
EN
LX
HX
XL
XH
XX
L
L
H
H
X
L
L
L
L
H
*On next negative transition of CLK0 or CLK1
X = Don’t Care
Q
L
H
L
H
L*
Table 2. PIN DESCRIPTION
Open
Pin Number Name I/O Default
Description
1 Q0 LVPECL Output
Non−Inverted Differential Clock Output
2 Q0 LVPECL Output
Inverted Differential Clock Output
3 Q1 LVPECL Output
Non−Inverted Differential Clock Output
4 Q1 LVPECL Output
Inverted Differential Clock Output
5 Q2 LVPECL Output
Non−Inverted Differential Clock Output
6 Q2 LVPECL Output
Inverted Differential Clock Output
7 Q3 LVPECL Output
Non−Inverted Differential Clock Output
8 Q3 LVPECL Output
Inverted Differential Clock Output
9 Q4 LVPECL Output
Non−Inverted Differential Clock Output
10 Q4 LVPECL Output
Inverted Differential Clock Output
11 VEE
Power
Negative Supply Voltage
12
SEL LVCMOS / LVTTL
Low Clock Select Input. When HIGH, selects CLK1 input. When LOW,
Input
selects CLK0, CLK0 inputs. Internal Pull−down Resistor.
13 NC
No Connect
14
CLK0
Multi−Level Input
High
Inverted Differential Clock Input. Internal Pull−up Resistor.
15
CLK0
Multi−Level Input
Low Non−Inverted Differential Clock Input. Internal Pull−down Resistor.
16
CLK1
LVCMOS/LVTTL
Low Single−ended Clock Input. Internal Pull−down Resistor.
Input
17 NC
No Connect
18 VCC
Power
Positive Supply Voltage
19 EN LVCMOS/LVTTL Low Synchronous Clock Enable Input. When Low, outputs are enabled.
Input
When High, outputs are disabled Low. Internal Pull−down Resistor.
20 VCC
Power
Positive Supply Voltage
All VCC and VEE pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with
0.01 mF to GND.
www.onsemi.com
2


Part Number NB3L853141
Description 2.5V/3.3V 1:5 LVPECL Fanout Buffer
Maker ON Semiconductor
Total Page 10 Pages
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