900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




  ON Semiconductor Electronic Components Datasheet  

NB3N65027 Datasheet

3.3V Programmable 3-PLL Clock Synthesizer

No Preview Available !

NB3N65027
3.3V Programmable 3-PLL Clock
Synthesizer with
6 LVTTL/LVCMOS Outputs w/OE
The NB3N65027 is a LVCMOS PLLsynthesized clock generator.
It accepts a 10 MHz to 27 MHz clock or fundamental mode crystal as
the reference source and drives three independent, low noise
phaselocked loops (PLLs).
Control lines ACSx, BCSx and CCS will select their appropriate
bank output frequencies. ACS1 and BCS1 are twolevel
LVTTL/LVCMOS inputs, High and Low. ACS0, BCS0 and CCS are
threelevel LVCMOS inputs, High, Mid and Low.
The NB3N65027 has three independent LVTTL/LVCMOS output
banks of two outputs each. Banks A and B offer a 1X and a 1/2X
output. Using a 25 MHz crystal, the selectable output frequencies
range from 16 2/3 MHz to 133 1/3 MHz. A 12.5 MHz crystal offers
from 8 1/3 MHz to 66 2/3 MHz. In addition, the NB3N65027 will
generate a buffered reference LVTTL/LVCMOS output, REFOUT,
10 MHz to 27 MHz. See Tables 2 through 9 for the variety of available
output frequencies. The OE pin, when set LOW, will disable the output
drivers to high impedance.
The NB3N65027 operates from a single +3.3 V supply across the
operating temperature range from 40°C to +85°C, and is offered in a
QSOP20 RoHS compliant package.
The NB3N65027 provides the optimum combination of low cost,
flexibility, and high performance for Network, PCI and SDRAM
applications.
Features
http://onsemi.com
MARKING DIAGRAM
3N65027
AWLYWWG
QSOP20
CASE 492AC
3N65027 = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = PbFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
12.5 MHz or 25 MHz Fundamental Crystal or Clock
Input
Six Output Clocks with Selectable Frequencies
Buffered Crystal Reference Output
SDRAM Frequencies of 67, 83, 100, and 133 MHz
Operating Range: VCC = 3.3 V ±10%
QSOP20 Package, 150 mil
40°C to +85°C Ambient Operating Temperature
These Devices are PbFree and are RoHS Compliant
LVCMOS with 25 mA Output Drive Capability at TTL
Levels
VDD
ACS1
ACS0
BCS1
BCS0
CCS
25 or 12.5 MHz
crystal or clock
X1/ICLK
X2 CLX2
PLLA
PLLB
PLLC
Buffer /
Oscillator
Clock
Synthesis
and Control
Circuitry
CLX1
GND
Figure 1. Simplified Logic Diagram
CLKA1
B2 CLKA2
CLKB1
B2 CLKB2
CLKC1
CLKC2
REFOUT
OE (all outputs)
© Semiconductor Components Industries, LLC, 2011
June, 2011 Rev. 2
1
Publication Order Number:
NB3N65027/D


  ON Semiconductor Electronic Components Datasheet  

NB3N65027 Datasheet

3.3V Programmable 3-PLL Clock Synthesizer

No Preview Available !

NB3N65027
ACS0
X2
X1/ICLK
VDD
ACS1
GND
CLKC1
CLKC2
CLKB2
CLKB1
1
2
3
4
5
6
7
8
9
10
20 BCS1
19 BCS0
18 REFOUT
17 CLKA1
16 VDD
15 OE
14 GND
13 CLKA2
12 NC
11 CCS
Figure 2. Pinout: QSOP20 (Top View)
Table 1. PIN DESCRIPTION (Note 1)
Pin Number Pin Name
Pin Type
Pin Description
1
ACS0
TriLevel Input A Clock Select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3.
2
X2
Input
Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock
input.
3
X1/ICLK
Input
Crystal or Clock input connection. If a clock input is used, drive it into X1 and leave X2
unconnected.
4
VDD
Power
Connect to +3.3 V. Must be the same as pin 16.
5
ACS1
TwoLevel Input A Clock Select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal
pullup.
6
GND
Power
Connect to ground.
7
CLKC1
Output
Output Clock C1. Depends on setting of CCS per table on page 3.
8
CLKC2
Output
Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1.
9
CLKB2
Output
Output Clock B2. Depends on setting of BCS1, 0 per table on page 3.
10
CLKB1
Output
Output Clock B1. Depends on setting of BCS1, 0 per table on page 3.
11
CCS
TriLevel Input Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3.
12 NC
No Connect
13
CLKA2
Output
Output Clock A2. Depends on setting of ACS1, 0 per table on page 3.
14
GND
Power
Connect to ground.
15 OE
Input
Output enable. Tristates all outputs when low. Internal pullup.
16
VDD
Power
Connect to +3.3 V. Must be the same as pin 4.
17
CLKA1
Output
Output Clock A1. Depends on setting of ACS1, 0 per table on page 3.
18
REFOUT
Output
Buffered reference clock output. Same frequency as crystal or clock input.
19
BCS0
TriLevel Input B Clock Select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3.
20
BCS1
TwoLevel Input B Clock Select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal
pullup.
1. All VDD and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2


Part Number NB3N65027
Description 3.3V Programmable 3-PLL Clock Synthesizer
Maker ON Semiconductor
Total Page 7 Pages
PDF Download

NB3N65027 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 NB3N65027 3.3V Programmable 3-PLL Clock Synthesizer
ON Semiconductor





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy