NB3RL02 Datasheet, ON Semiconductor

* Low Additive Noise:
* −149 dBc/Hz at 10 kHz Offset Phase Noise
* 0.37 ps (rms) Output Jitter
* Limited Output Slew Rate for EMI Reduction (1 ns to 5 ns/.

* Cellular Phones
* Global Positioning Systems (GPS) www.onsemi.com MARKING DIAGRAMS WLCSP8 CASE 499BQ RLYYW.

Ball No. Name A1 VBATT A2 CLK_OUT1 B1 VLDO B2 CLK_REQ1 C1 MCLK_IN C2 CLK_REQ2 D1 GND D2 CLK_OUT2 I/O Description I Input to internal LDO O Clock output 1 O 1.8 V supply for NB3RL02 and external TCXO I Clock request from pe.