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NB3RL02 Datasheet

Low Phase-Noise Two-Channel Clock Fanout Buffer

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NB3RL02
Low Phase-Noise
Two-Channel Clock Fanout
Buffer
The NB3RL02 is a lowskew, low jitter 1:2 clock fanout buffer,
ideal for use in portable endequipment, such as mobile phones. With
integrated LDO and output control circuitry.
The MCLK_IN pin has an AC coupling capacitor and will directly
accept a square or sine wave clock input, such as a temperature
compensated crystal oscillator (TCXO). The minimum acceptable
input amplitude of the sine wave is 300 mV peaktopeak.
The two clock outputs are enabled by control inputs CLK_REQ1
and CLK_REQ2.
The NB3RL02 has an integrated LowDropOut (LDO) voltage
regulator which accepts input voltages from 2.3 V to 5.5 V and outputs
1.8 V at Iout = 50 mA. This 1.8 V supply is externally available to
provide regulated power to peripheral devices, such as a TCXO.
The adaptive clock output buffers offer controlled slewrate over a
wide capacitive loading range which minimizes EMI emissions,
maintains signal integrity, and minimizes ringing caused by signal
reflections on the clock distribution lines.
The NB3RL02 is offered in a 0.4 mm pitch waferlevelchipscale
(WLCS) package (0.8 mm x 1.6 mm) and is optimized for very low
standby current consumption.
Features
Low Additive Noise:
149 dBc/Hz at 10 kHz Offset Phase Noise
0.37 ps (rms) Output Jitter
Limited Output Slew Rate for EMI Reduction
(1 ns to 5 ns/Rise/Fall Time for 1050 pF Loads)
Regulated 1.8 V Output Supply Available for External Clock Source,
ie. TCX0
UltraSmall Package:
8ball: 0.4 mm Pitch WLCS (0.8 mm x 1.6 mm)
ESD Performance Exceeds JESD 22
2000 V HumanBody Model (A114A)
200 V Machine Model (A115A)
1000 V ChargedDevice Model (JESD22C101A Level III)
These are PbFree Devices
Applications
Cellular Phones
Global Positioning Systems (GPS)
http://onsemi.com
MARKING
DIAGRAMS
WLCSP8
CASE 499BQ
RLYYWW
G
RL = Specific Device Code
YY = Year
WW = Work Week
G = PbFree Package
LOGIC DIAGRAM
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
July, 2011 Rev. 1
1
Publication Order Number:
NB3RL02/D
Datasheet pdf - http://www.DataSheet4U.net/


  ON Semiconductor Electronic Components Datasheet  

NB3RL02 Datasheet

Low Phase-Noise Two-Channel Clock Fanout Buffer

No Preview Available !

www.DataSheet.co.kr
NB3RL02
12
A A1 A2
B B1 B2
C C1 C2
D D1 D2
(Package Flip Chip)
Die Pads Face Down on PCB
Figure 1. Pinout (Top View)
Table 1. PIN DESCRIPTION
Ball No.
Name
A1 VBATT
A2 CLK_OUT1
B1 VLDO
B2 CLK_REQ1
C1 MCLK_IN
C2 CLK_REQ2
D1 GND
D2 CLK_OUT2
I/O Description
I Input to internal LDO
O Clock output 1
O 1.8 V supply for NB3RL02 and external TCXO
I Clock request from peripheral 1
I Master clock input
I Clock request from peripheral 2
Ground
O Clock output 2
Table 2. FUNCTION TABLE
Inputs
CLK_REQ1 CLK_REQ2
LL
LH
HL
HH
MCLK_IN
X
CLK
CLK
CLK
CLK_OUT1
L
L
CLK
CLK
Outputs
CLK_OUT2
L
CLK
L
CLK
VLDO
0V
1.8 V
1.8 V
1.8 V
http://onsemi.com
2
Datasheet pdf - http://www.DataSheet4U.net/


Part Number NB3RL02
Description Low Phase-Noise Two-Channel Clock Fanout Buffer
Maker ON Semiconductor
Total Page 8 Pages
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