900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




  ON Semiconductor Electronic Components Datasheet  

NB3V8312C Datasheet

Ultra-Low Jitter Low Skew 1:12 LVCMOS - LVTTL Fanout Buffer

No Preview Available !

NB3V8312C
Ultra-Low Jitter, Low Skew
1:12 LVCMOS/LVTTL Fanout
Buffer
The NB3V8312C is a high performance, low skew L VCMOS
fanout buffer which can distribute 12 ultra low jitter clocks from an
LVCMOS/LVTTL input up to 250 MHz.
http://onsemi.com
The 12 LVCMOS output pins drive 50 W series or parallel
terminated transmission lines. The outputs can also be disabled to a
high impedance (tristated) via the OE input, or enabled when High.
The NB3V8312C provides an enable input, CLK_EN pin, which
synchronously enables or disables the clock outputs while in the LOW
state. Since this input is internally synchronized to the input clock,
changing only when the input is LOW , potential output glitching or
runt pulse generation is eliminated.
LQFP32
FA SUFFIX
CASE 873A
1 32
QFN32
MN SUFFIX
CASE 488AM
Separate V DD core and V DDO output supplies allow the output
buffers to operate at the same supply as the V DD (VDD = V DDO) or
from a lower supply voltage. Compared to single supply operation,
VDDO
VDD
GND
Q0
dual supply operation enables lower power consumption and
outputlevel compatibility.
The VDD core supply voltage can be set to 3.3 V , 2.5 V or 1.8 V,
while the VDDO output supply voltage can be set to 3.3 V , 2.5 V, or
1.8 V, with the constraint that VDD VDDO.
This buffer is ideally suited for various networking, telecom, server
CLK_EN
RPU
D
Q
Q1
Q2
Q3
Q4
and storage area networking, RRU LO reference distribution, medical
and test equipment applications.
Features
Power Supply Modes:
CLK
RPD
Q5
Q6
Q7
VDD (Core) / VDDO (Outputs)
3.3 V
/ 3.3 V
3.3 V
/ 2.5 V
3.3 V
/ 1.8 V
Q8
Q9
Q10
2.5 V
2.5 V
1.8 V
/ 2.5 V
/ 1.8 V
/ 1.8 V
RPU
OE
Q11
250 MHz Maximum Clock Frequency
Figure 1. Simplified Logic Diagram
Accepts LVCMOS, LVTTL Clock Inputs
LVCMOS Compatible Control Inputs
12 LVCMOS Clock Outputs
Synchronous Clock Enable
ORDERING AND MARKING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
Output Enable to High Z State Control
150 ps Max. Skew Between Outputs
Temp. Range 40°C to +85°C
32pin LQFP and QFN Packages
Applications
Networking
Telecom
Storage Area Network
These are PbFree Devices
End Products
Servers
Routers
Switches
© Semiconductor Components Industries, LLC, 2013
August, 2013 Rev. 0
1
Publication Order Number:
NB3V8312C/D
http://www.Datasheet4U.com


  ON Semiconductor Electronic Components Datasheet  

NB3V8312C Datasheet

Ultra-Low Jitter Low Skew 1:12 LVCMOS - LVTTL Fanout Buffer

No Preview Available !

NB3V8312C
GND
VDD
CLK_EN
CLK
GND
OE
VDD
GND
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4
NB3V8312C
21
5 20
6 19
7 18
8
91
0 11
12 13 14 15
17
16
Q4
VDDO
Q5
GND
Q6
VDDO
Q7
GND
GND
VDD
CLK_EN
CLK
GND
OE
VDD
GND
1
2
3
4
5
6
7
8
NB3V8312C
Exposed
Pad (EP)
24 Q4
23 VDDO
22 Q5
21 GND
20 Q6
19 VDDO
18 Q7
17 GND
Figure 2. LQFP32 Pinout Configuration
(Top View)
Figure 3. QFN32 Pinout Configuration
(Top View)
Table 1. PIN DESCRIPTION
Pin Name
Open
I/O Default
Description
1, 5, 8, 12, 16, 17,
21, 25, 29
GND
Power
Ground, Negative Power Supply
2, 7
VDD
Power
Positive Supply for Core and Inputs
3
CLK_EN
Input
High
Synchronous Clock Enable Input. When High, outputs
are enabled. When Low, outputs are disabled Low.
Internal Pullup Resistor.
4
CLK
Input
Low Singleended Clock input; LVCMOS/LVTTL. Internal
Pulldown Resistor.
6
OE
Input
High
Output Enable. Internal Pullup Resistor.
9, 11, 13, 15, 18,
20, 22, 24, 26, 28,
30, 32
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output
Singleended LVCMOS/LVTTL outputs
10, 14, 19, 23, 27,
31
VDDO
Power
Positive Supply for Outputs
EP − − The Exposed Pad (EP) on the package bottom is ther-
mally connected to the die for improved heat transfer
out of package. The exposed pad must be attached to a
heatsinking conduit. The pad is connected to the die
and must only be connected electrically to GND on the
PC board.
1. All VDD, VDDO and GND pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with
0.01 mF to GND.
http://onsemi.com
2


Part Number NB3V8312C
Description Ultra-Low Jitter Low Skew 1:12 LVCMOS - LVTTL Fanout Buffer
Maker ON Semiconductor
Total Page 11 Pages
PDF Download

NB3V8312C Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 NB3V8312C Ultra-Low Jitter Low Skew 1:12 LVCMOS - LVTTL Fanout Buffer
ON Semiconductor





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy