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NB3W1200L - 3.3V 100/133MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer

Download the NB3W1200L datasheet PDF. This datasheet also covers the NB3N1200K variant, as both devices belong to the same 3.3v 100/133mhz differential 1:12 hcsl or push-pull clock zdb/fanout buffer family and are provided as variant models within a single manufacturer datasheet.

General Description

The NB3N1200K and NB3W1200L differential clock buffers are DB1200Z and DB1200ZL compliant and are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point to

point clocks to multiple agents.

Key Features

  • 12 Differential Clock Output Pairs @ 0.7 V.
  • HCSL Compatible Outputs for NB3N.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (NB3N1200K-ONSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number NB3W1200L
Manufacturer onsemi
File Size 197.23 KB
Description 3.3V 100/133MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer
Datasheet download datasheet NB3W1200L Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NB3N1200K, NB3W1200L 3.3 V 100/133 MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle Description The NB3N1200K and NB3W1200L differential clock buffers are DB1200Z and DB1200ZL compliant and are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point−to−point clocks to multiple agents. The device is capable of distributing the reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz frequency operation. The NB3N1200K and NB3W1200L utilize pseudo−external feedback topology to achieve low input−to output delay variation.