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  ON Semiconductor Electronic Components Datasheet  

NB3W1200L Datasheet

3.3V 100/133MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer

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NB3N1200K, NB3W1200L
3.3 V 100/133 MHz
Differential 1:12 HCSL or
Push-Pull Clock ZDB/Fanout
Buffer for PCle
Description
The NB3N1200K and NB3W1200L differential clock buffers are
DB1200Z and DB1200ZL compliant and are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel® QuickPath Interconnect
(Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and
Intel Scalable Memory Interconnect (Intel SMI) applications. The
VCO of the device is optimized to support 100 MHz and 133 MHz
frequency operation. The NB3N1200K and NB3W1200L utilize
pseudo−external feedback topology to achieve low input−to output
delay variation. The NB3N1200K is configured with the HCSL buffer
type, while the NB3W1200L is configured with the low−power
NMOS Push−Pull buffer type.
Features
12 Differential Clock Output Pairs @ 0.7 V
HCSL Compatible Outputs for NB3N1200K
Low−Power NMOS Push−Pull Compatible Outputs for NB3W1200L
Optimized 100 MHz and 133 MHz Operating Frequencies to Meet
The Next Generation PCIe Gen2/Gen3/Gen4 and Intel QPI & UPI
Phase Jitter
DB1200Z and DB1200ZL Compliant
3.3 V ±5% Supply Voltage Operation
Fixed−Feedback for Lowest Input−To−Output Delay Variation
SMBus Programmable Configurations to Allow Multiple Buffers in a
Single Control Network
PLL Bypass Configurable for PLL or Fanout Operation
Programmable PLL Bandwidth
2 Tri−level Addresses Selection (9 SMBUS Addresses)
Individual OE Control Pin for Each of 12 Outputs
50 ps Max Output−to−Output Skew Performance
50 ps Max Cycle−to−Cycle Jitter (PLL mode)
100 ps Input to Output Delay Variation Performance
QFN 64−pin Package, 9 mm x 9 mm
Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
EMI
0°C to +70°C Ambient Operating Temperature
These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
64 1
QFN64
MN SUFFIX
CASE 485DH
MARKING DIAGRAMS
1
NB3N
1200K
AWLYYWWG
1
NB3W
1200L
AWLYYWWG
NB3x1200x= Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package Shipping
NB3N1200KMNG
QFN−64
(Pb−Free)
260 Units /
Tray
NB3N1200KMNTXG QFN−64 1000 / Tape &
(Pb−Free)
Reel
NB3W1200LMNG
QFN−64
(Pb−Free)
260 Units /
Tray
NB3W1200LMNTXG QFN−64 1000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
July, 2017 − Rev. 3
1
Publication Order Number:
NB3N1200K/D


  ON Semiconductor Electronic Components Datasheet  

NB3W1200L Datasheet

3.3V 100/133MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer

No Preview Available !

12
OE_[11:0]#
CLK_IN
CLK_IN#
NB3N1200K, NB3W1200L
SSC Compatible
PLL
MUX
FB_OUT*
FB_OUT#*
DIF_[11:0]
DIF_[11:0]#
100M_133M#
HBW_BYPASS_LBW#
SA_0
SA_1
PWRGD/PWRDN#
SDA
SCL
Control
Logic
* FB_OUT pins are for NB3N1200K only; they are NC for NB3W1200L
** IREF pin is for NB3N1200K only; it is NC for NB3W1200L
Figure 1. Simplified Block Diagram
IREF**
RREF
www.onsemi.com
2


Part Number NB3W1200L
Description 3.3V 100/133MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer
Maker ON Semiconductor
Total Page 26 Pages
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