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  ON Semiconductor Electronic Components Datasheet  

NB6LQ572M Datasheet

2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator

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NB6LQ572M
2.5V / 3.3V Differential 4:1
Mux w/Input Equalizer to
1:2 CML Clock/Data Fanout
/ Translator
MultiLevel Inputs w/ Internal Termination
Description
The NB6LQ572M is a high performance differential 4:1 Clock /
Data input multiplexer and a 1:2 CML Clock / Data fanout buffer that
operates up to 6 GHz / 8 Gbps respectively with a 2.5 V or 3.3 V
power supply.
Each INx/INx input pair incorporates a fixed Equalizer Receiver,
which when placed in series with a Clock / Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB6L572M, which is pincompatible to the
NB6LQ572M.
The differential Clock / Data inputs have internal 50 W termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB6LQ572M incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
CML output copies of Clock or Data.
As such, the NB6LQ572M is ideal for SONET, GigE, Fiber
Channel, Backplane and other Clock/Data distribution applications.
The two differential CML outputs will swing 400 mV when
externally loaded and terminated with a 50 W resistor to VCC and are
optimized for low skew and minimal jitter.
The NB6LQ572M is offered in a low profile 5x5mm 32pin QFN
PbFree package. Application notes, models, and support
www.DatdaoSchuemet4eUnt.caotimon are available at www.onsemi.com. The NB6LQ572M
is a member of the ECLinPS MAXfamily of high performance
clock products.
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB6L
Q572M
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
Features
Input Data Rate > 8 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 6 GHz Typical
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:2 CML Outputs, < 15 ps max
4:1 MultiLevel Mux Inputs, accepts LVPECL, CML
LVDS
Input EQ for Backplane and Cable Interconnect
Compensation
150 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV PeaktoPeak,
Typical
Operating Range: VCC = 2.375 V to 3.6 V with
GND = 0 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN32 Package, 5mm x 5mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
© Semiconductor Components Industries, LLC, 2009
November, 2009 Rev. 0
1
Publication Order Number:
NB6LQ572M/D


  ON Semiconductor Electronic Components Datasheet  

NB6LQ572M Datasheet

2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator

No Preview Available !

NB6LQ572M
Multilevel Inputs
LVPECL, LVDS, CML
IN0
VT0
50 W
50 W
IN0
VREFAC0
IN1
VT1
50 W
50 W
IN1
VREFAC1
IN2
VT2
IN2
50 W
50 W
VREFAC2
IN3
VT3
50 W
50 W
IN3
VREFAC3
EQ0
0
EQ1
EQ2
1
4:1 MUX
2
EQ3
3
SEL0
SEL1
Figure 1. Simplified Block Diagram
CML Outputs
Q0
Q0
Q1
Q1
Exposed
Pad (EP)
32 31 30 29 28 27 26 25
IN0 1
24 GND
VT0 2
VREFAC0 3
IN0 4
www.DataSheIeNt14U.c5om
VT1 6
VREFAC1 7
IN1 8
NB6LQ572M
23 VCC
22 Q1
21 Q1
20 VCC
19 NC
18 SEL1
17 VCC
9 10 11 12 13 14 15 16
Table 1. INPUT SELECT FUNCTION TABLE
SEL1*
SEL0*
Clock / Data Input Selected
0 0 IN0 Input Selected
0 1 IN1 Input Selected
1 0 IN2 Input Selected
1 1 IN3 Input Selected
*Defaults HIGH when left open.
Figure 2. Pinout: QFN32 (Top View)
http://onsemi.com
2


Part Number NB6LQ572M
Description 2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator
Maker ON Semiconductor
Total Page 10 Pages
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