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  ON Semiconductor Electronic Components Datasheet  

NB6N11S Datasheet

Input to LVDS Fanout Buffer /Translator

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NB6N11S
3.3 V 1:2 AnyLevelE Input
to LVDS Fanout Buffer /
Translator
Description
The NB6N11S is a differential 1:2 Clock or Data Receiver and will
accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL,
or LVDS. These signals will be translated to LVDS and two identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N11S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N11S has a wide input common mode range from
GND + 50 mV to VCC 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6N11S is ideal for
translating a variety of differential or singleended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N11S is functionally equivalent to the EP11, LVEP11,
SG11 or 7L11M devices and is offered in a small, 3 mm X 3 mm,
16QFN package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB6N11S is a member of the ECLinPS MAXfamily of high
performance products.
Features
Maximum Input Clock Frequency > 2.0 GHz
www.DataSheet4U.com
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
These are PbFree Devices
http://onsemi.com
1
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6N
11S
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTD Q0
D
D
VTD
Figure 1. Logic Diagram
Q1
Q1
Device DDJ = 10 ps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2231 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2006
May, 2006 Rev. 0
1
Publication Order Number:
NB6N11S/D


  ON Semiconductor Electronic Components Datasheet  

NB6N11S Datasheet

Input to LVDS Fanout Buffer /Translator

No Preview Available !

NB6N11S
VCC VCC VCC VCC
16 15 14 13
Exposed Pad (EP)
Q0 1
Q0 2
Q1 3
Q1 4
NB6N11S
12 VTD
11 D
10 D
9 VTD
5678
VCC NC VEE VEE
Figure 3. NB6N11S Pinout, 16pin QFN (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
1 Q0
LVDS Output
Noninverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2 Q0
LVDS Output
Inverted D output. Typically loaded with 10 W receiver termination resistor
across differential pair.
3 Q1
LVDS Output
Noninverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4 Q1
LVDS Output
Inverted D output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5 VCC
6 NC
Positive Supply Voltage
No Connect
7 VEE
Negative Supply Voltage
8 VEE
Negative Supply Voltage
9 VTD
Internal 50 W termination pin for D
10
D
LVPECL, CML, LVDS,
Inverted Differential Clock/Data Input (Note 1)
LVCMOS, LVTTL
11
D
LVPECL, CML, LVDS,
Noninverted Differential Clock/Data Input (Note 1)
LVCMOS, LVTTL
12 VTD
Internal 50 W termination pin for D
13 VCC
Positive Supply Voltage
14 VCC
Positive Supply Voltage
15 VCC
Positive Supply Voltage
16 VCC
Positive Supply Voltage
EP Exposed pad. The exposed pad (EP) on the package bottom must be
attached to a heatsinking conduit. The exposed pad may only be
electrically connected to VEE.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to selfoscillation.
http://onsemi.com
2


Part Number NB6N11S
Description Input to LVDS Fanout Buffer /Translator
Maker ON Semiconductor
Total Page 9 Pages
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