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NB6N11S Datasheet Input to LVDS Fanout Buffer/Translator

Manufacturer: onsemi

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Datasheet Details

Part number NB6N11S
Manufacturer onsemi
File Size 314.24 KB
Description Input to LVDS Fanout Buffer/Translator
Download NB6N11S Download (PDF)

General Description

The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS.

These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively.

As such, the NB6N11S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications.

Overview

NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator.

Key Features

  • Maximum Input Clock Frequency > 2.0 GHz.
  • Maximum Input Data Rate > 2.5 Gb/s.
  • 1 ps Maximum of RMS Clock Jitter.
  • Typically 10 ps of Data Dependent Jitter.
  • 380 ps Typical Propagation Delay.
  • 120 ps Typical Rise and Fall Times.
  • Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and SG Devices.
  • These are Pb.
  • Free Devices www. onsemi. com 1 QFN.
  • 16 MN SUFFIX CASE 485G.

More Datasheets from onsemi

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