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NB6N14S Datasheet - ON Semiconductor

Differential Input to LVDS Fanout Buffer/Translator

NB6N14S Features

* Maximum Input Clock Frequency > 2.0 GHz

* Maximum Input Data Rate > 2.5 Gb/s

* 1 ps Maximum RMS Clock Jitter

* Typically 10 ps Data Dependent Jitter

* 380 ps Typical Propagation Delay

* 120 ps Typical Rise and Fall Times

* VREF_AC Reference O

NB6N14S General Description

Pin Name I/O Description 1 Q1 LVDS Output Non *inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 2 Q1 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 3 Q2 L.

NB6N14S Datasheet (367.51 KB)

Preview of NB6N14S PDF

Datasheet Details

Part number:

NB6N14S

Manufacturer:

ON Semiconductor ↗

File Size:

367.51 KB

Description:

Differential input to lvds fanout buffer/translator.
NB6N14S 3.3 V 1:4 AnyLevelt Differential Input to LVDS Fanout Buffer/Translator The NB6N14S is a differential 1:4 Clock or Data Receiver and will acce.

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TAGS

NB6N14S Differential Input LVDS Fanout Buffer Translator ON Semiconductor

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