NBSG14 Overview
MARKING DIAGRAMS The NBSG14 is a 1−to−4 clock/data distribution chip, optimized for ultra−low skew and jitter. Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.
NBSG14 Key Features
- Rev. 9
- ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input
- RSECL Output RSECL Output
- RSECL Output RSECL Output RSECL Output RSECL Output RSECL Output RSECL Output
- Description Internal 50 W Termination pin. See Table 2. Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW t
- 2 V- Noninverted Differential Output 3. Typically Terminated with 50 W to VTT = VCC
- 2 V- Positive Supply Voltage. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. I
- 2 V- Noninverted Differential Outpu