NCP1571 Datasheet | onsemi

Features http://onsemi. MARKING DIAGRAM 8 8 1 SOIC- 8 D SUFFIX CASE 751 1 A L Y W = Assembly Location = Wafer Lot = Year = Work Week 1571 ALYW - - - - - - - - - - - - - - - Pb- Free Package is Available 0.980 V ± 1.0% Reference Voltage V2 Control Topology 200 ns Transient Response Programmable Soft- Start Power Good Programmable Power Good Delay 40 ns Gate Rise and Fall Times (3.3 n F Load) Adaptive FET Non- Overlap Time Fixed 200 k Hz Oscillator Frequency Undervoltage Lockout Holds Both Gate Outputs Low On/Off Control Through Use of the P Pin Overvoltage Protection through Synchronous MOSFETs Synchronous N- Channel Buck Design Dual Supply, 12 V Control, 2- 7 V Power Source PIN CONNECTIONS VCC PWRGD PGDELAY P 1 8 GND VFB GATE(L) GATE(H) ORDERING INFORMATION Device NCP1571D NCP1571DR2 NCP1571DR2G Package SOIC- 8 SOIC- 8 SOIC- 8 (Pb- Free) Shipping† 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor ponents Industries, LLC, 2004 October, 2004 - Rev. 4 Publication Order Number NCP1571/D 12 V PWRGD VLOGIC R1 50 k C4 0.47 m F R4 10 PWRGD NCP1571 PGDELAY P C13 0.1 m F VFB VCC GND 100 p F C6 NTD4302 Q1 2.7 m H L1 + + + + 5.0 V 33 m F/8.0 V/1.6 Arms C1 + + C2 + C3 2.5 V/10 A GATE(L) GATE(H) NTD4302 Q2 5.1 k R3 C8 C9 C10 C11 GND C12 0.01 m F R5 3.3 k 56 m F/4.0 V/1.6 Arms SP- CAP 40 m W Figure 1. Applications Circuit MAXIMUM...