NCP9004 Datasheet | onsemi

Features http://onsemi. MARKING DIAGRAM 9- PIN FLIP- CHIP CSP FC SUFFIX CASE 499E 1 MAQ A Y WW G = Device Code = Assembly Location = Year = Work Week = Pb- Free Package MAQG AYWW PIN CONNECTIONS 9- Pin Flip- Chip CSP A1 INP B1 VP C1 INM A2 GND B2 VP C2 SD (Top View) A3 OUTM B3 GND C3 OUTP - Optimized PWM Output Stage: Filterless Capability - Efficiency up to 90% - - - - - - - - - - - - - - - Low 2.5 m A Typical Quiescent Current Large Output Power Capability: 1.4 W with 8.0 W Load and THD+N < 1% Wide Supply Voltage Range: 2.5- 5.5 V Operating Voltage High Performance, THD+N of 0.03% @ Vp = 5.0 V, RL = 8.0 W, Pout = 100 m W Excellent PSRR (- 65 d B): No Need for Voltage Regulation Surface Mounted Package 9- Pin Flip- Chip CSP (Sn Pb and Pb- Free) Fully Differential Design. Eliminates Two Input Coupling Capacitors Very Fast Turn On/Off Times with Advanced Rising and Falling Gain Technique External Gain Configuration Capability Internally Generated 250 k Hz Switching Frequency Short Circuit Protection Circuitry “Pop and Click” Noise Protection Circuitry ORDERING INFORMATION See detailed ordering and shipping information on page 16 of this data sheet. Cs Audio Input from DAC Ri Ri INP INM SD VP OUTM OUTP Applications Input from Microcontroller Cellular Phone Portable Electronic Devices PDAs and Smart Phones Portable puter GND Cs Ri 1.6 mm Ri 3.7 mm Solution Size © Semiconductor ponents Industries, LLC, 2006 August, 2006 - Rev. 2 Publication Order Number: NCP9004/D TYPICAL APPLICATION BATTERY Cs Rf Ri INP BYPASS Negative Differential Input Vp BYPASS INTERNAL BIASING OUTP Ri BYPASS INM Rf 300 k W SD Vih Vil RAMP GENERATOR OUTM Vp Shutdown Control Positive Differential Input Figure 1. Typical Application PIN DESCRIPTION Pin No. A1 A2 A3 B1 B2 B3 C1 C2 Symbol INP GND OUTM Vp Vp GND INM SD Type...