NLSF3T125
Features
- High Speed: t PD = 3.8 ns (Typ) at VCC = 5.0 V
- Low Power Dissipation: ICC = 4.0 m A (Max) at TA = 25°C
- TTL- patible Inputs: VIL = 0.8 V; VIH = 2.0 V
- Power Down Protection Provided on Inputs
- Balanced Propagation Delays
- Designed for 2.0 V to 5.5 V Operating Range
- Low Noise: VOLP = 0.8 V (Max)
- Pin and Function patible with Other Standard Logic Families
- Latchup Performance Exceeds 300 m A
- ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
- Chip plexity: 72 FETs or 18 Equivalent Gates
- These Devices are Pb- Free and are Ro HS pliant
FUNCTION TABLE
Inputs
Output Y H L Z http://onsemi.
1 QFN- 16 CASE 485G
MARKING DIAGRAM
NLSF3 T125 ALYWG
NLSF3T125 = Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb- Free...
