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NV24C16MUW - 16-Kb EEPROM

Download the NV24C16MUW datasheet PDF. This datasheet also covers the NV24C02MUW variant, as both devices belong to the same 16-kb eeprom family and are provided as variant models within a single manufacturer datasheet.

General Description

The NV24C02/04/08/16 are EEPROM Serial 2/4/8/16

Automotive Grade 1 devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each.

All devices support the Standard (100 kHz) and Fast (400 kHz) I2C protocol.

Key Features

  • Automotive AEC.
  • Q100 Grade 1 (.
  • 40°C to +125°C) Qualified.
  • Supports Standard, Fast and Fast.
  • Plus I2C Protocol.
  • 2.5 V to 5.5 V Supply Voltage Range.
  • 16.
  • Byte Page Write Buffer.
  • Fast Write Time (4 ms max).
  • Hardware Write Protection for Entire Memory.
  • Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA).
  • Low power CMOS Technology.
  • More than 1,000,000 Program/Erase.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (NV24C02MUW-ONSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by onsemi

Part Number Description
NV24C16LV 16-Kb CMOS Serial EEPROM
NV24C128MUW EEPROM
NV24C128WF EEPROM
NV24C02MUW 2-Kb EEPROM
NV24C04LV 4-Kb CMOS Serial EEPROM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
EEPROM Serial 2/4/8/16-Kb I2C Automotive Grade 1 in Wettable Flank UDFN-8 Package NV24C02MUW, NV24C04MUW, NV24C08MUW, NV24C16MUW Description The NV24C02/04/08/16 are EEPROM Serial 2/4/8/16−Kb I2C Automotive Grade 1 devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each. All devices support the Standard (100 kHz) and Fast (400 kHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non−volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count.