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  ON Semiconductor Electronic Components Datasheet  

SC14046B Datasheet

Phase Locked Loop

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SC14046B
Phase Locked Loop
The SC14046B phase locked loop contains two phase comparators,
a voltagecontrolled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCAin and
PCBin. Input PCAin can be used directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The selfbias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate)
provides a digital error signal PC1out, and maintains 90° phase shift at
the center frequency between PCAin and PCBin signals (both at 50%
duty cycle). Phase comparator 2 (with leading edge sensing logic)
provides digital error signals, PC2out and LD, and maintains a 0°
phase shift between PCAin and PCBin signals (duty cycle is
immaterial). The linear VCO produces an output signal VCOout
whose frequency is determined by the voltage of input VCOin and the
capacitor and resistors connected to pins C1A, C1B, R1, and R2. The
sourcefollower output SFout with an external resistor is used where
the VCOin signal is needed but no loading can be tolerated. The inhibit
input Inh, when high, disables the VCO and source follower to
minimize standby power consumption. The zener diode can be used to
assist in power supply regulation.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltagetofrequency conversion and motor speed control.
Features
Buffered Outputs Compatible with MHTL and LowPower TTL
Diode Protection on All Inputs
Supply Voltage Range = 3.0 to 18 V
PinforPin Replacement for CD4046B
Phase Comparator 1 is an Exclusive OR Gate and is Duty Cycle Limited
Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle
Limited
PbFree Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD DC Supply Voltage Range
Vin Input Voltage Range (All Inputs)
Iin DC Input Current, per Pin
PD Power Dissipation, per Package
(Note 1)
0.5 to +18.0
0.5 to VDD + 0.5
± 10
500
V
V
mA
mW
TA Operating Temperature Range
55 to +125
°C
Tstg Storage Temperature Range
65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “DW” Packages: – 7.0 mW/_C From 65_C To 125_C
http://onsemi.com
MARKING
DIAGRAM
16
SOIC16
DW SUFFIX
CASE 751G
14046BG
AWLYYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this highimpedance circuit. For proper op-
eration, Vin and Vout should be constrained to the range
VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused out-
puts must be left open.
*For additional information on our PbFree strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2008
August, 2008 Rev. 0
1
Publication Order Number:
SC14046B/D


  ON Semiconductor Electronic Components Datasheet  

SC14046B Datasheet

Phase Locked Loop

No Preview Available !

SC14046B
BLOCK DIAGRAM
PIN ASSIGNMENT
PCAin 14
SELF BIAS
CIRCUIT
PHASE
COMPARATOR 1
2  PC1out
LD
PC1out
1
2
16 VDD
15 ZENER
PCBin 3
PHASE
COMPARATOR 2
13 PC2out
1  LD
PCBin 3
14 PCAin
VCOin 9
VDD = PIN 16
VSS = PIN 8
VOLTAGE
CONTROLLED
OSCILLATOR
(VCO)
4  VCOout
11 R1
12 R2
6  C1A
7  C1B
VCOout
INH
C1A
4
5
6
13 PC2out
12 R2
11 R1
INH 5
VSS
SOURCE FOLLOWER
10 SFout
15 ZENER
C1B 7
VSS 8
10 SFout
9 VCOin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic
Symbol
VDD
Vdc
55_C
Min Max
Output Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin = VDD or 0
“0” Level VOL
5.0
10
15
0.05
0.05
0.05
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin = 0 or VDD
“1” Level VOH
5.0 4.95
10 9.95
15 14.95
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage (Note 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 13.5 or 1.5 Vdc)
“0” Level
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 0.5 or 4.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
“1” Level
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 9.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 13.5 Vdc)
Source
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOL = 1.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current
Sink
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current
(Per Package) Inh = PCAin = VDD,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎZener = VCOin = 0 V, PCBin = VDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎor 0 V, Iout = 0 mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (Note 3)
(Inh = “0”, fo = 10 kHz, CL = 50 pF,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎR1 = 1.0 MW, R2 = R RSF = ,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎand 50% Duty Cycle)
VIL
VIH
IOH
IOL
Iin
Cin
IDD
IT
5.0 1.5
10 3.0
15 4.0
5.0 3.5
10 7.0
15 11
5.0 – 1.2
5.0 – 0.25
10 – 0.62
15 – 1.8
5.0 0.64
10 1.6
15 4.2
15 ± 0.1
−−−
5.0 5.0
10 10
15 20
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ2. Noise immunity specified for worstcase input combination.
Min
4.95
9.95
14.95
25_C
Typ
0
0
0
5.0
10
15
Max
0.05
0.05
0.05
2.25 1.5
4.50 3.0
6.75 4.0
3.5 2.75
7.0 5.50
11 8.25
– 1.0
– 0.2
– 0.5
– 1.5
0.51
1.3
3.4
– 1.7
– 0.36
– 0.9
– 3.5
0.88
2.25
8.8
± 0.00001
5.0
0.005
0.010
0.015
± 0.1
7.5
5.0
10
20
IT = (1.46 mA/kHz) f + IDD
IT = (2.91 mA/kHz) f + IDD
IT = (4.37 mA/kHz) f + IDD
125_C
Min Max
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11
– 0.7
– 0.14
– 0.35
– 1.1
0.36
0.9
2.4
± 1.0
150
300
600
Unit
Vdc
Vdc
Vdc
Vdc
mAdc
mAdc
mAdc
pF
mAdc
mAdc
Noise Margin for both “1” and “0” level =
3. To Calculate Total Current in General:
1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc
ǒ Ǔ ǒ ǓIT [ 2.2 x VDD
VCOin – 1.65
R1
+
VDD 1.35 3/4
R2
+ 1.6 x
VCOin – 1.65
RSF
3/4
+ 1 x 103 (CL + 9) VDD f +
ǒ Ǔ1 x 101 VDD2
100% Duty Cycle of PCAin
100
+ IQ
where: IT in mA, CL in pF, VCOin, VDD in Vdc, f in kHz, and
R1, R2, RSF in MW, CL on VCOout.
http://onsemi.com
2


Part Number SC14046B
Description Phase Locked Loop
Maker ON Semiconductor
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