The LS161A/163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature.
The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs.
Key Features
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is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC.
Full PDF Text Transcription for SN74LS161A (Reference)
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SN74LS161A, SN74LS163A BCD Decade Counters/ 4−Bit Binary Counters The LS161A/163A are high-speed 4-bit synchronous counters. They are edge-triggered, synchronously preset...
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it synchronous counters. They are edge-triggered, synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and other applications. The LS161A and LS163A count modulo 16 (binary). The LS161A has an asynchronous Master Reset (Clear) input that overrides, and is independent of, the clock and all other control inputs. The LS163A has a Synchronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge.
SN74LS161A Datasheet
