PM73123 Datasheet | PMC-Sierra

PM73123 .. AAL1gator™-8 8 Link CES/DBCES AAL1 SAR Features - Supports eight structured/unstructured T1, E1 links or one unstructured DS3, E3 or STS-1/STM-0 link over an AAL1 CBR ATM network. - pliant with ATM Forum's CES (AFVTOA-0078), and ITU-T I.363.1. - Supports up to 256 VCs. - Supports n x 64 (consecutive channels) and m x 64 (nonconsecutive channels) structured data format with channel associated signaling (CAS) support. - Internal E1/T1 clock synthesizers provided for each line which can be controlled via internal synchronous residual time stamp (SRTS) or an internal programmable weighted moving average adaptive clocking algorithm in unstructured mode. Clock synthesizers can also be controlled externally to provide customization of SRTS or adaptive clocking methods. - Provides transparent transmission of CCS and CAS and termination of CAS signaling. - pliant with ATM Forum's Dynamic Bandwidth Circuit Emulation Service (DBCES) AF-VTOA-0085. Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis. - Supports AAL0 mode, selectable on a per VC basis. - Provides transmit and receive buffers which can be used for OAM cells as well as any other user-generated cells such as AAL5 cells for ATM signaling. - Provides an optional 8/16-bit Any PHY™ slave interface. - Provides a three cell FIFO for UTOPIA loopback support on a per VC basis or a global basis. TRANSMIT SECTION - Provides individually enabled per-VC data and signaling conditioning in the transmit cell direction and per DS0 data and signaling conditioning in the transmit line direction. Includes DS3 AIS conditioning support in both directions. - Provides per-VC configuration of time slots allocated, CAS support, partial cell size, data and signaling conditioning, ATM Cell header definition. - Generates AAL1 sequence numbers, pointers and SRTS values in accordance with ITU-T I.363.1....