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PJDLC15 - ULTRA LOW CAPACITANCE DUAL TRANSIET VOLTAGE SUPPRESSOR

This page provides the datasheet information for the PJDLC15, a member of the PJDLC03 ULTRA LOW CAPACITANCE DUAL TRANSIET VOLTAGE SUPPRESSOR family.

Features

  • Maximum capacitance @ 0 Vdc Bias of 1.2 pF between terminals 1-3 or terminals 2-3.
  • IEC61000-4-2 esd 15kV Air, 8kV contact compliance.
  • In compliance with EU RoHS 2002/95/EC directives 0.056(1.40) 0.047(1.20) 0.079(2.00) 0.070(1.80).

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Datasheet preview – PJDLC15

Datasheet Details

Part number PJDLC15
Manufacturer PanJit Semiconductor
File Size 129.73 KB
Description ULTRA LOW CAPACITANCE DUAL TRANSIET VOLTAGE SUPPRESSOR
Datasheet download datasheet PJDLC15 Datasheet
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Full PDF Text Transcription

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PJDLC03~PJDLC24 VOLTAGE 3.3 to 24 Volts POWER 400 Watts 0.006(0.15)MIN. 0.008(0.20) 0.003(0.08) 0.044(1.10) 0.035(0.90) 0.020(0.50) 0.013(0.35) ULTRA LOW CAPACITANCE DUAL TRANSIET VOLTAGE SUPPRESSOR FOR HIGH SPEED DATA LINES This transient overvoltage suppressor is intended to prodect sensitive equipment againset electrostatic discharge events as well to offer a minmum lnsertion loss in data transmission lines in communications ports used in portable consumer, computing and networking applicatons. This dual transient voltage suppressor comes in a single SOT-23, offering borard space reduction, where the application requires it. 0.120(3.04) 0.110(2.80) FEATURES • Maximum capacitance @ 0 Vdc Bias of 1.
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