Figure 3. Pin Configuration
Table 2. Pin Descriptions
1 VDD Nominal 3 V supply connection.1
2 GND Ground connection. 3
3 RF1 RF port. 2
CMOS or TTL logic level:
High = RF1 to RF2 signal path
Low = RF1 isolated from RF2
5 GND Ground connection. 3
6 RF2 RF port. 2
Notes: 1. A bypass capacitor should be placed as close as possible
to the pin.
2. Both RF pins must be DC blocked by an external capacitor
or held at 0 VDC.
3. The exposed pad must be soldered to the ground plane for
proper switch performance.
Table 3. Absolute Maximum Ratings
Symbol Parameter/Condition Min Max
VDD Power supply voltage
VI Voltage on CTRL input
Input power (50 Ω),
(Human Body Model)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE4246 in
the 6-lead 3x3 DFN package is MSL1.
The PE4246 high-isolation SPST RF Switch is
designed to support a variety of applications
where high isolation performance is demanded
and a non-reflective input and output is desired.
This switch is able to replace multiple lesser
performing switches in a very small 3x3 mm DFN
Table 4. Operating Ranges
VDD Power Supply
IDD Power Supply Current
(VDD = 3 V, VCNTL = 3 V)
TOP Operating temperature
Control Voltage High
Control Voltage Low
Typ Max Unit
33 40 μA
Table 5. Control Logic Truth Table
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
RF1 to RF2
RF1 isolated from RF2
The control logic input pin (CTRL) is typically driven by
a 3-volt CMOS logic level signal, and has a threshold of
50% of VDD. For flexibility to support systems that have
5-volt control logic drivers, the control logic input has
been designed to handle a 5-volt logic HIGH signal. (A
minimal current will be sourced out of the VDD pin when
the control logic input voltage level exceeds VDD.)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 3.
Unlike conventional CMOS devices, UltraCMOS™ de-
vices are immune to latch-up.
©2003-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
Document No. 70-0090-09 │ UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. patents: http://patents.psemi.com