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Peregrine Semiconductor

PE4307 Datasheet Preview

PE4307 Datasheet

RF Digital Attenuator

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Product Description
The PE4307 is a high linearity, 5-bit RF Digital Step
Attenuator (DSA) covering a 15.5 dB attenuation range in
0.5 dB steps. The device is pin compatible with the PE430x
series. This 75-ohm RF DSA provides both parallel (latched
or direct mode) and serial CMOS control interface, operates
on a single 3-volt supply and maintains high attenuation
accuracy over frequency and temperature. It also has a
unique control interface that allows the user to select an
initial attenuation state at power-up. The PE4307 exhibits
very low insertion loss and low power consumption. This
functionality is delivered in a 4x4 mm QFN footprint.
The PE4307 is manufactured on Peregrine’s UltraCMOS®
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
Switched Attenuator Array
RF Input
RF Output
Product Specification
PE4307
75Ω RF Digital Attenuator
5-bit, 15.5 dB, 1 2000 MHz
Features
Attenuation: 0.5 dB steps to 15.5 dB
Flexible parallel and serial programming
interfaces
Latched or direct mode
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
75Ω impedance
Pin compatible with PE430x series
Packaged in a 20-lead 4x4 mm QFN
Figure 2. Package Type
20-lead 4x4 mm QFN
Parallel Control 5
Serial Control 3
Power-Up Control 1
Control Logic Interface
71-0007
Table 1. Electrical Specifications @ +25°C, VDD = 3.0V
Parameter
Test Condition
Frequency
Minimum Typical
Maximum
Unit
Operation Frequency
1
2000
MHz
Insertion Loss1
1 MHz ≤ 1.2 GHz
Attenuation Accuracy
Any Bit or Bit
Combination
1 MHz ≤ 1.2 GHz
1 dB Compression3,4
1 MHz ≤ 1.2 GHz
Input IP31,2,4
Two-tone inputs up to
+18 dBm
1 MHz ≤ 1.2 GHz
Return Loss
Zo = 75 ohms
1 MHz ≤ 1.2 GHz
Switching Speed
50% control to 0.5 dB
of final value
Notes: 1. Device Linearity will begin to degrade below 1 MHz
2. Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency
3. Note Absolute Maximum in Table 3
4. Measured in a 50Ω system
-
-
30
-
10
-
1.4 1.95 dB
-
±(0.15 + 4% of atten setting)
Not to exceed +0.25 dB
dB
dB
34 - dBm
52 - dBm
13 - dB
- 1 s
Document No. 70-0161-05 www.psemi.com
©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 1 of 11




Peregrine Semiconductor

PE4307 Datasheet Preview

PE4307 Datasheet

RF Digital Attenuator

No Preview Available !

PE4307
Product Specification
Figure 15. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
N/C 1
RF1 2
Data 3
Clock 4
LE 5
20-lead
QFN
4x4mm
Exposed Solder Pad
15 C8
14 RF2
13 P/S
12 Vss/GND
11 GND
Symbol
VDD
VI
TST
PIN
VESD
Parameter/Condition
Power supply voltage
Voltage on any input
Storage temperature range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min Max Unit
-0.3 4.0
-0.3
VDD+
0.3
-65 150
V
V
°C
+30 dBm
500 V
Table 4. Operating Ranges
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
Pin
Name
N/C
RF1
Data
Clock
LE
VDD
N/C
PUP2
VDD
GND
GND
Vss/GND
P/S
RF2
C8
C4
C2
GND
C1
C0.5
GND
Description
No connect
RF port (Note 1)
Serial interface data input (Note 4)
Serial interface clock input
Latch Enable input (Note 2)
Power supply pin
No connect
Power-up selection bit
Power supply pin
Ground connection
Ground connection
Negative supply voltage or GND
connection (Note 3)
Parallel/Serial mode select
RF port (Note 1)
Attenuation control bit, 8 dB
Attenuation control bit, 4 dB
Attenuation control bit, 2 dB
Ground connection.
Attenuation control bit, 1 dB
Attenuation control bit, 0.5 dB
Ground for proper operation
Notes: 1. Both RF ports must be held at 0 VDC or DC blocked with an external
series capacitor
2. Latch Enable (LE) has an internal 100 kΩ resistor to VDD
3. Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and disable
internal negative voltage generator
4. Place a 10 kΩ resistor in series, as close to pin as possible to avoid
frequency resonance. See “Resistor on 3” paragraph
Parameter
VDD Power Supply
Voltage
IDD Power Supply
Current
Digital Input High
Digital Input Low
Digital Input Leakage
Input Power
Temperature range
Min Typ Max
2.7 3.0 3.3
0.7xVDD
-40
100
0.3xVDD
1
+24
85
Unit
V
μA
V
V
μA
dBm
°C
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
Switching Frequency
The PE4307 has a maximum 25 kHz switching rate.
Resistor on Pin 3
A 10 kΩ resistor on the input to Pin 3 (see Figure 5)
will eliminate package resonance between the RF
input pin and the digital input. Specified attenuation
error versus frequency performance is dependent
upon this condition.
©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0161-05 UltraCMOS® RFIC Solutions
Page 2 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com


Part Number PE4307
Description RF Digital Attenuator
Maker Peregrine Semiconductor
Total Page 11 Pages
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