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Peregrine Semiconductor

PE64904 Datasheet Preview

PE64904 Datasheet

UltraCMOS Digitally Tunable Capacitor

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Product Description
The PE64904 is a DuNE™-enhanced Digitally Tunable
Capacitor (DTC) based on Peregrine’s UltraCMOS®
technology. DTC products provide a monolithically
integrated impedance tuning solution for demanding RF
applications.
The PE64904 offers high RF power handling and
ruggedness, while meeting challenging harmonic and
linearity requirements.
This highly versatile product can be used in series or shunt
configurations to support a wide variety of tuning circuit
topologies.
The device is controlled through the widely supported
3-wire (SPI compatible) interface. All decoding and biasing
is integrated on-chip and no external bypassing or filtering
components are required.
Peregrine’s DuNE™ technology enables excellent linearity
and exceptional harmonic performance. DuNE devices
deliver performance superior to GaAs devices with the
economy and integration of conventional CMOS.
Figure 1. Functional Block Diagram
Product Specification
PE64904
UltraCMOS® Digitally Tunable Capacitor
(DTC) 100 - 3000 MHz
Features
3-wire (SPI compatible) Serial Interface
with built-in bias voltage generation and
ESD protection
DuNE™-enhanced UltraCMOS® device
5-bit 32-state Digitally Tunable Capacitor
Series configuration C = 0.60 - 4.60 pF
(7.7:1 tuning ratio) in discrete 129 fF steps
Shunt configuration C = 1.14 - 5.10 pF
(4.6:1 tuning ratio) in discrete 129 fF steps
High RF Power Handling (up to 38 dBm,
30 Vpk RF) and High Linearity
Wide power supply range (2.3 to 3.6V)
and low current consumption
(typ. 140 μA at 2.6V)
Excellent 1.5 kV HBM ESD tolerance
on all pins
2 x 2 x 0.45 mm QFN package
Applications include:
Tunable Filter Networks
Tunable Antennas
RFID
Tunable Matching Networks
Phase Shifters
Wireless Communications
RF+
ESD
RF-
ESD
Figure 2. Package Type
10L 2 x 2 x 0.45 mm QFN package
Serial
Interface
CMOS Control
Driver and ESD
DOC-87399-1
71-0066-01
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11




Peregrine Semiconductor

PE64904 Datasheet Preview

PE64904 Datasheet

UltraCMOS Digitally Tunable Capacitor

No Preview Available !

PE64904
Product Specification
Table 1. Electrical Specifications @ 25°C, VDD = 2.6V
Parameter
Configuration
Condition
Operating Frequency Range
Both
Minimum Capacitance
Series
Shunt
State = 00000, 100 MHz (RF+ to RF-)
State = 00000, 100 MHz (RF+ to Grounded RF-)
Maximum Capacitance
Series
Shunt
State = 11111, 100 MHz (RF+ to RF-)
State = 11111, 100 MHz (RF+ to Grounded RF-)
Parasitic Capacitance
Series
All States, 100 MHz (RF+ to GND, RF- to GND)
Tuning Ratio
Series
Shunt
100 MHz
100 MHz
Step Size
Both
5 bits (32 states), constant step size (100 MHz)
Equivalent Series Resistance
Series
State = 00000
State = 11111
Quality Factor (Cmin)1
Shunt
100 MHz, with Ls removed
1 GHz, with Ls removed
2 GHz, with Ls removed
3 GHz, with Ls removed
Quality Factor (Cmax)1
Shunt
100 MHz, with Ls removed
1 GHz, with Ls removed
2 GHz, with Ls removed
3 GHz, with Ls removed
Self Resonant Frequency
Harmonics (2fo)2
Harmonics (3fo)2
Shunt
Series
State 00000
State 11111
100 MHz - 3 GHz
100 MHz - 3 GHz
Min
100
0.49
0.90
3.78
4.19
Typ
0.60
1.10
4.60
5.10
0.5
7.7:1
4.6:1
0.129
1.40
1.33
10
35
32
25
27
25
11
6
7.5
3.1
Max
3000
0.71
1.30
5.45
6.00
-36
-36
Units
MHz
pF
pF
pF
pF
Ω
GHz
dBm
dBm
Input Intercept Point (2nd Order)
Series
100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing
105 dBm
Input Intercept Point (3rd Order)
Series
100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing
65
Switching Time3, 4
Both
50% CTRL to 10/90% delta capacitance between any two
states
Start-up Time3
Both
Time from VDD within specification to all performances within
specification
Wake-up Time3, 4
Both
State change from standby mode to RF state to all perfor-
mances within specification
Notes: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit.
Q = XC/R = (X-XL)/R, where X = XL+XC , XL = 2*pi*f*L, XC = -1/(2*pi*f*C), which is equal to removing the effect of parasitic inductance LS.
2. In series or shunt between 50 Ω ports. Pulsed RF input with 4620 µs period, 50% duty cycle, measured per 3GPP TS 45.005.
3. DC path to ground at RF+ and RF- must be provided to achieve specified performance.
4. State change activated on falling edge of SEN following data word.
dBm
12 µs
100 µs
100 µs
©2018 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
DOC-87399-1


Part Number PE64904
Description UltraCMOS Digitally Tunable Capacitor
Maker Peregrine Semiconductor
Total Page 11 Pages
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