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Peregrine Semiconductor

PE9701 Datasheet Preview

PE9701 Datasheet

Integer-N PLL Rad Hard

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Product Description
Peregrine’s PE9701 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The device
is designed for superior phase noise performance while
providing an order of magnitude reduction in current
consumption, when compared with existing commercial
space PLLs.
The PE9701 features a 10/11 dual modulus prescaler,
counters, and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
The PE9701 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10-9 errors per bit / day. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
excellent RF performance and intrinsic radiation tolerance.
Figure 1. Block Diagram
Product Specification
PE9701
3000 MHz UltraCMOS™ Integer-N PLL
Rad Hard for Space Applications
Features
3.0 GHz operation
÷10/11 dual modulus prescaler
Internal phase detector with charge
pump
Serial, parallel or hardwired
programmable
Ultra-low phase noise
SEU < 10-9 errors / bit-day
100 Krad (Si) total dose
44-lead CQFJ
Fin Prescaler
Fin 10/11
D(7:0)
8
Sdata
Primary
20-bit
Latch 20
Pre_en
M(6:0)
A(3:0)
R(3:0)
fr
Secon-
dary
20-bit
Latch
20
20
20
16
Main
Counter
13
66
R Counter
fp
PD_U
Phase
Detector
PD_D
Charge
Pump
CP
fc
Document No. 70-0035-02 www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13




Peregrine Semiconductor

PE9701 Datasheet Preview

PE9701 Datasheet

Integer-N PLL Rad Hard

No Preview Available !

PE9701
Product Specification
Figure 2. Pin Configurations (Top View)
Figure 3. Package Type
44-lead CQFJ
D0, M0
D1, M1
D2, M2
D3, M3
VDD
VDD
S_W R, D4, M4
Sdata, D5, M5
Sclk, D6, M6
FSELS, D7, Pre_en
GND
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
fc
VDD_fc
N/C
CP
VDD
Cext
VDD
Dout
VDD_fp
fp
GND
Table 1. Pin Descriptions
Pin No. Pin Name Interface Mode
1 VDD
ALL
2 R0
Direct
3 R1
Direct
4 R2
Direct
5 R3
Direct
6
GND
ALL
D0
7
M0
8 D1
M1
9 D2
M2
10 D3
M3
11 VDD
12 VDD
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
ALL
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
S_WR
Serial
13
D4
Parallel
M4 Direct
Input
Input
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Same as pin 1.
Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data is transferred to the secondary register on S_WR or Hop_WR
rising edge.
Parallel data bus bit4
M Counter bit4
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 13
Document No. 70-0035-02 UltraCMOS™ RFIC Solutions


Part Number PE9701
Description Integer-N PLL Rad Hard
Maker Peregrine Semiconductor
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PE9701 Datasheet PDF






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