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Peregrine Semiconductor

PE9702 Datasheet Preview

PE9702 Datasheet

3.0 GHz Integer-N PLL

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Product Description
Peregrine’s PE9702 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
device is designed for superior phase noise performance
while providing an order of magnitude reduction in
current consumption, when compared with existing
commercial space PLLs.
The PE9702 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial
or parallel interface and can also be directly hard wired.
The PE9702 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10-9 errors per bit / day. Fabricated in Peregrine’s
patented UTSi® (Ultra Thin Silicon) CMOS technology,
the PE9702 offers excellent RF performance and intrinsic
radiation tolerance.
Figure 1. Block Diagram
Fin Prescaler
Fin 10 / 11
D(7:0)
8
Sdata
Primary
20-bit
Latch 20
Pre_en
M(6:0)
A(3:0)
R(3:0)
fr
Secon-
dary
20-bit
Latch
20
20
20
16
Main
Counter
13
66
R Counter
ADVANCE INFORMATION
PE9702
3.0 GHz Integer-N PLL for Rad
Hard Applications
Features
3.0 GHz operation
÷10/11 dual modulus prescaler
Internal phase detector
Serial, parallel or hardwired
programmable
Ultra-low phase noise
SEU < 10-9 errors / bit-day
100 Krad (Si) total dose
44-lead CQFJ
fp
Phase
Detector
PD_U
PD_D
fc
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 15




Peregrine Semiconductor

PE9702 Datasheet Preview

PE9702 Datasheet

3.0 GHz Integer-N PLL

No Preview Available !

Figure 2. Pin Configuration
D0, M0
D1, M1
D2, M2
D3, M3
VDD
VDD
S_WR, D4, M4
Sdata, D5, M5
Sclk, D6, M6
FSELS, D7, Pre_en
GND
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
fc
VDD_fc
PD_U
PD_D
VDD
Cext
VDD
Dout
VDD_fp
fp
GND
PE9702
Advance Information
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
Pin Name
VDD
R0
R1
R2
R3
GND
D0
M0
D1
M1
D2
M2
D3
M3
VDD
VDD
Interface Mode
ALL
Direct
Direct
Direct
Direct
ALL
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
ALL
13
S_WR
Serial
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Same as pin 1.
Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary
register data is transferred to the secondary register on S_WR or Hop_WR rising edge.
Copyright Peregrine Semiconductor Corp. 2003
Page 2 of 15
File No. 70/0036~00C | UTSi CMOS RFIC SOLUTIONS


Part Number PE9702
Description 3.0 GHz Integer-N PLL
Maker Peregrine Semiconductor
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PE9702 Datasheet PDF






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