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PI6C557-06 - 1:4 HCSL PCIe Buffer

General Description

HCSL outputs compliant to PCIe® Gen 1, 2 and 3 standards.

device has selectable reference inputs to provide flexibility in system design.

Key Features

  • ÎÎ1:4 HCSL clock buffer ÎÎPCIe® Gen 1, 2 and 3 compliant ÎÎSelectable reference inputs ÎÎCycle-to-Cycle Jitter.

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Full PDF Text Transcription for PI6C557-06 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for PI6C557-06. For precise diagrams, and layout, please refer to the original PDF.

Features ÎÎ1:4 HCSL clock buffer ÎÎPCIe® Gen 1, 2 and 3 compliant ÎÎSelectable reference inputs ÎÎCycle-to-Cycle Jitter <70ps ÎÎOutput-to-Output Skew <35ps ÎÎ3.3V supply ...

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cle-to-Cycle Jitter <70ps ÎÎOutput-to-Output Skew <35ps ÎÎ3.3V supply voltage ÎÎTSSOP-20 package ÎÎIndustrial Temperature Applications ÎÎServers ÎÎEmbedded computing systems ÎÎNetworking systems Block Diagram OE SRCIN1 SRCIN1# SRCIN2 SRCIN2# REFSEL PD# PI6C557-06 1:4 HCSL PCIe® Buffer Description The PI6C557-06 is a high performance PCIe® buffer with four HCSL outputs compliant to PCIe® Gen 1, 2 and 3 standards. The device has selectable reference inputs to provide flexibility in system design.

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