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Pericom Semiconductor Corporation

PI6C48535-11 Datasheet Preview

PI6C48535-11 Datasheet

3.3V Low Skew 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer

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Features
• Maximum operation frequency: 500MHz
• 4 pair of differential LVPECL outputs
• Selectable CLK and crystal inputs
• CLK accepts LVCMOS, LVTTL input level
• Output Skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.5ns (maximum)
• 3.3V power supply
• Pin-to-pin compatible to ICS8535-11
• Operating Temperature: -40oC to 85oC
• Packaging (Pb-free & Green available):
- 20-pin TSSOP (L)
Block Diagram
CLK_EN
CLK
Xtal1
Xtal2
0
1
D
Q
LE
CLK_SEL
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PI6C48535-11
3.3V Low Skew 1-to-4
Crystal/LVCMOS to LVPECL Fanout Buffer
Description
The PI6C48535-11 is a high-performance low-skew LVPECL
fanout buffer. PI6C48535-11 features selectable of single-ended
clock or crystal inputs and translates to four LVPECL outputs.
The CLK input accepts LVCMOS or LVTTL signals. The outputs
are synchronized with input clock during asynchronous assertion
/deassertion of CLK_EN pin. PI6C48535-11 is ideal for crystal or
LVCMOS/LVTTL to LVPECL translation. Typical clock transla-
tion and distribution applications are data-communications and
telecommunications.
Pin Diagram
VEE 1
CLK_EN 2
CLK_SEL 3
CLK 4
Q0 NC 5
nQ0 Xtal1 6
Xtal2 7
Q1 NC 8
nQ1 NC 9
VCC 10
Q2
nQ2
Q3
nQ3
20 Q0
19 NQ0
18 VCC
17 Q1
16 NQ1
15 Q2
14 NQ2
13 VCC
12 Q3
11 NQ3
1
PS9738
05/27/04




Pericom Semiconductor Corporation

PI6C48535-11 Datasheet Preview

PI6C48535-11 Datasheet

3.3V Low Skew 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer

No Preview Available !

PI6C48535-11
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Crystal/LVCMOS to LVPECL Fanout Buffer
Pin Description
Name
Pin #
Type
Description
VEE 1 P Connect to Negative power supply
CLK_EN
Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx
2 I_PU outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 50KΩ
pull up.
CLK_SEL
3
I_PD
Clock select input. When high, selects CLK1 input. When low, selects CLK0 input.
LVCMOS/LVTTL level with 50KΩ pull down.
CLK
4 I_PD LVCMOS / LVTTL clock input
Xtal1,
Xtal2
6, 7
Crystal input and output
NC 5, 8, 9
No internal connection.
VCC
10, 13,
18
P Connect to 3.3V
Q3, nQ3
11, 12
O Differential output pair, LVPECL interface level.
Q2, nQ2
Q1, nQ1
Q0, nQ0
14, 15
16, 17
19, 20
O Differential output pair, LVPECL interface level.
O Differential output pair, LVPECL interface level.
O Differential output pair, LVPECL interface level.
Notes:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up
Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
R_pullup
Input Pullup Resistance
R_pulldown Input Pulldown Resistance
Conditions
Min.
Typ.
Max.
Units
4 pF
50 KΩ
50 KΩ
Control Input Function Table
Inputs
Outputs
CLK_EN
0
CLK_SEL
0
Selected Source
CLK
Q0:Q3
Diasbled: Low
nQ0:nQ3
Diasbled: High
01
Xtal1, Xtal2
Disabled: Low
Disabled: High
10
CLK
Enabled
Enabled
11
Xtal1, Xtal2
Enabled
Enabled
Notes:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
2
PS9738
05/27/04


Part Number PI6C48535-11
Description 3.3V Low Skew 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer
Maker Pericom Semiconductor Corporation
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PI6C48535-11 Datasheet PDF






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Pericom Semiconductor Corporation





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