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74ALVT162823 Datasheet Preview

74ALVT162823 Datasheet

18-bit bus-interface D-type flip-flop

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74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with
30 termination resistors; 3-state
Rev. 02 — 11 August 2005
Product data sheet
1. General description
The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra
packages required to buffer existing registers and provide extra data width for wider data
or address paths of buses carrying parity.
The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and
master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed
systems.
The registers are fully edge-triggered. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the
flip-flop.
The 74ALVT162823 is designed with 30 series resistance in both the pull-up and
pull-down output structures. This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus receivers or transmitters.
2. Features
s Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
s 5 V I/O compatible
s Ideal where high speed, light loading or increased fan-in are required with MOS
microprocessors
s Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
s Live insertion and extraction permitted
s Power-up 3-state
s Power-up reset
s Output capability: +12 mA to 12 mA
s Outputs include series resistance of 30 making external termination resistors
unnecessary
s Latch-up protection:
x JESD78: exceeds 500 mA
s ESD protection:
x MIL STD 883, method 3015: exceeds 2000 V
x Machine Model: exceeds 200 V




Philips

74ALVT162823 Datasheet Preview

74ALVT162823 Datasheet

18-bit bus-interface D-type flip-flop

No Preview Available !

Philips Semiconductors
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
3. Quick reference data
Table 1: Quick reference data
Tamb = 25 °C.
Symbol Parameter
Conditions
tPLH propagation delay CL = 50 pF; VCC = 2.5 V
nCP to nQx
CL = 50 pF; VCC = 3.3 V
tPHL propagation delay CL = 50 pF; VCC = 2.5 V
nCP to nQx
CL = 50 pF; VCC = 3.3 V
Ci
input capacitance
VI = 0 V or VCC
Co output capacitance VI/O = 0 V or 3.0 V
ICC quiescent supply outputs disabled;
current
VCC = 2.5 V
outputs disabled;
VCC = 3.3 V
Min Typ Max Unit
- 3.7 - ns
- 2.9 - ns
- 2.8 - ns
- 2.3 - ns
- 3 - pF
- 9 - pF
- 40 - µA
- 70 - µA
4. Ordering information
Table 2: Ordering information
Type number
Package
Temperature range Name
74ALVT162823DL 40 °C to +85 °C SSOP56
74ALVT162823DGG 40 °C to +85 °C TSSOP56
Description
plastic shrink small outline package; 56 leads; body
width 7.5 mm
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
Version
SOT371-1
SOT364-1
74ALVT162823_2
Product data sheet
Rev. 02 — 11 August 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2 of 20


Part Number 74ALVT162823
Description 18-bit bus-interface D-type flip-flop
Maker Philips
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