• Part: 74F225
  • Description: 16X5 asynchronous FIFO
  • Manufacturer: Philips Semiconductors
  • Size: 122.16 KB
Download 74F225 Datasheet PDF
Philips Semiconductors
74F225
74F225 is 16X5 asynchronous FIFO manufactured by Philips Semiconductors.
FEATURES - Independent synchronous inputs and outputs - Organized as 16 words of 5 bits - DC to 25MHz data rate - 3- State outputs - Cascadable in word- width and depth direction DESCRIPTION This 80- bit active element First- In- First- Out (FIFO) is a monolithic Schottky- clamped transistor- transistor logic (STTL) array organized as 16- words of 5- bits each. A memory system using the ’F225 can be easily expanded in multiples of 16- words of 5- bits as shown in Figure 1. The 3- State outputs controlled by a single enable input (OE) make bus connection and multiplexing simple. The ’F225 processes data in a parallel format at any desired clock rate from DC to 25MHz. Status of the ’F225 is provided by three outputs, Input Ready (IR), Unload Clock Output (UNCPOUT) and Output Ready (OR). The data outputs are non- inverting with respect to the data inputs and are disabled when the OE input is High. When OE is Low, the data outputs are enabled to function as totem- pole outputs. TYPICAL SUPPLY CURRENT ( TOTAL) 65m A TYPE 74F225 TYPICAL f MAX 25MHz ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F225N N74F225D PKG DWG # 20- pin plastic DIP 20- pin plastic SOL SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS CPA, CPB D0 - D4 OE UNCPIN MR IR UNCPOUT Q0 - Q4 DESCRIPTION Load clock A and load clock B inputs Data inputs Output enable input (active- Low) Unload clock input Master reset input (active- Low) Input ready output Unload clock output (active- Low) Data outputs 74F (U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 50/33 50/33 150/40 50/33 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 1.0m A/20m A 1.0m A/20m A 3.0m A/24m A 1.0m A/20m A OR Output ready output NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low state. RESET MODE A High- to- Low transition on the Master Reset (MR) input invalidates all data stored in the FIFO by clearing the control...