74F378 Datasheet | Philips Semiconductors

FEATURES - 6-bit high-speed parallel register - Positive edge-triggered D-type inputs - Fully buffered mon Clock and Enable inputs - Input clamp diodes limit high speed termination effects - Fully TTL and CMOS patible DESCRIPTION The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transformed to the corresponding flop-flop’s Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation. TYPE 74F378 TYPICAL fmax 100MHz TYPICAL SUPPLY CURRENT (TOTAL) 35m A ORDERING INFORMATION DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F378N N74F378D PKG DWG # 16- pin plastic DIP 16- pin plastic SO SOT38-4 SOT109-1 PIN CONFIGURATION E 1 Q0 2 D0 3 D1 4 Q1 5 D2 6 Q2 7 GND 8 16 V CC 15 Q5 14 D5 13 D4 12 Q4 11 D3 10 Q3 9 CP SF00927 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS D0 - D5 CP E Data inputs Clock pulse input (active rising edge) Enable input (active low) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 1.0m A/20m A Q0 - Q5 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low state. 1989 Oct 05 853- 0067 97804 Philips Semiconductors Product specification Hex D flip-flop with enable LOGIC SYMBOL 3 4 6 11 13 14 IEC/IEEE SYMBOL 1 9 3 2D 4 6 Q0 Q1 Q2 Q3 Q4 Q5 11 13 2 5 7 10 12 15 14 15 10 12 G1 1C2 2 5 7 D0 D1 D2 D3 D4 D5 9 1 CP E VCC = Pin 16 GND = Pin 8 SF00916 SF00917 LOGIC...