74F399 Datasheet | Philips Semiconductors

FEATURES 74F398- ,74F399 - Select inputs from two data sources - Fully positive edge-triggered - Both True and plementary outputs- 74F398 DESCRIPTION The 74F398 and 74F399 are the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A mon Select input determines which of two 4-bit words is accepted. The selected data enters the flip-flops on the rising edge of the clock. The 74F399 is the 16-pin version of the 74F398, with only the true (Qn) outputs of the flip-flops available. The 74F398 and 74F399 are high speed quad 2-port registers. They select 4 bits of data from either of two sources (Ports) under control of a mon select input (S). The selected data is transferred to a 4-bit output register synchronous with the Low-to-High transition of the Clock input (CP). The 4-bit D-type output register is fully edge-triggered. The Data inputs (I0n, I1n) and Select input (S) must be stable only a setup time prior to and hold time after the Low-to-High transition of the Clock input for predictable operation. The 74F398 has both Q and Q outputs. TYPICAL SUPPLY CURRENT (TOTAL) 25m A 22m A PIN CONFIGURATION - 74F398 S Qa Qa I0a I1a I1b I0b Qb Qb GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Qd Qd I0d I1d I1c I0c Qc Qc CP SF00947 PIN CONFIGURATION - 74F399 S Qa I0a I1a I1b I0b Qb GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Qd I0d I1d I1c I0c Qc CP TYPE 74F398 74F399 TYPICAL f MAX 120MHz 120MHz ORDERING INFORMATION DESCRIPTION 16-pin plastic DIP 16-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F399N N74F399D PKG DWG # SOT38-4 SOT109-1 SF00951 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS I0a, I0b, I0c, I0d I1a, I1b, I1c, I1d S CP Qa, Qb, Qc, Qd Qa, Qb, Qc, Qd DESCRIPTION Data inputs from source 0 Data inputs from source 1 mon Select input Clock input (active rising edge) Register true outputs Register plementary outputs (74F398) 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 50/33...