74F712A Datasheet | Philips Semiconductors

FEATURES for 74F711A/74F711-1 - Consists of five 2-to-1 Multiplexers - High impedance PNP base inputs for reduced loading (20µA in High and Low states) applications - Designed for address multiplexing of dynamic RAM and other - Output inverting/non-inverting option - 30W termination impedance on each output - 74F711-1 - Outputs sink 64m A (74F711A only) FEATURES for 74F712A/74F712-1 TYPE 74F711A 74F711-1 74F712A 74F712-1 TYPICAL PROPAGATION DELAY 6.0ns 6.5ns 6.5ns 6.5ns - Consists of five 3-to-1 Multiplexers - High impedance PNP base inputs for reduced loading (20µA in High and Low states) applications - Designed for address multiplexing of dynamic RAM and other - 30W termination impedance on each output - 74F712-1 - Outputs sink 64m A (74F712A only) DESCRIPTION The 74F711A/74F711-1 consist of five 2-to-1 multiplexers designed for address multiplexing of dynamic RAMs and other multiplexing applications. The 74F711A has a mon select (S) input, an Output Enable (OE) input and an Output Inverting (INV) input to control the 3-State outputs. The outputs source 15m A and sink 64m A. The 74F711-1 is the same as the 74F711A except that is has a 30W termination impedance on each output to reduce line noise and the 3-State outputs sink 5m A. When the inverting input (INV) is Low, the input data path is inverted. ORDERING INFORMATION DESCRIPTION 20-Pin Plastic DIP 24-Pin Plastic Slim DIP (300 mil) 20-Pin Plastic SOL 24-Pin Plastic SOL MERCIAL RANGE VCC = 5V ± 10% Tamb = 0° C to +70°C N74F711AN, N74F711-1N N74F712AN, N74F712-1N N74F711AD, N74F711-1D N74F712AD, N74F712-1D PKG DWG # SOT146-1 SOT222-1 SOT163-1 SOT137-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Dna, Dnb S 74F711A/ 74F711-1 OE INV Q0 - Q4 Q0 - Q4 Dna, Dnb, Dnc 74F712A/ 74F712-1 S0, S1 Q0 - Q4 Q0 - Q4 Data inputs Select input Output Enable input (active Low) Output inverting...