Triple 3-input NAND gate
• Output capability: standard
• ICC category: SSI
The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT10 provide the 3-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
propagation delay nA, nB, nC to nY
power dissipation capacitance per gate
CL = 15 pF; VCC = 5 V
notes 1 and 2
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fO) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V.
See “74HC/HCT/HCU/HCMOS Logic Package Information”.