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Philips

74HC160 Datasheet Preview

74HC160 Datasheet

Presettable synchronous BCD decade counter

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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT160
Presettable synchronous BCD
decade counter; asynchronous
reset
Product specification
File under Integrated Circuits, IC06
December 1990




Philips

74HC160 Datasheet Preview

74HC160 Datasheet

Presettable synchronous BCD decade counter

No Preview Available !

Philips Semiconductors
Presettable synchronous BCD decade
counter; asynchronous reset
Product specification
74HC/HCT160
FEATURES
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive-edge triggered clock
Asynchronous reset
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT160 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT160 are synchronous presettable decade
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q0 to Q3) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0 to Q3) to LOW level regardless
of the levels at CP, PE, CET and CEP inputs (thus
providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
fmax = t--P-----(-m-----a--x---)------(--C-----P------t--o-----T----C----1)-----+------t--S---U-----(--C-----E----P-----t--o-----C----P-----)
QUICK REFERENCE DATA
GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns
SYMBOL PARAMETER
TYPICAL
CONDITIONS
HC HCT
tPHL propagation delay CL = 15 pF;
CP to Qn
VCC = 5 V
19 21
CP to TC
21 24
MR to Qn
21 23
MR to TC
21 26
CET to TC
14 14
tPLH propagation delay
CP to Qn
CP to TC
CET to TC
19 21
21 20
14 7
fmax maximum clock
frequency
61 31
CI input capacitance
3.5 3.5
CPD power dissipation notes 1 and 2
capacitance per
39 34
package
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
MHz
pF
pF
Notes
1. CPD is used to determine the
dynamic power dissipation
(PD in µW):
PD = CPD × VCC2 × fi +
(CL × VCC2 × fo)
where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of
outputs
CL = output load capacitance in
pF
VCC = supply voltage in V
2. For HC the condition is
VI = GND to VCC
For HCT the condition is
VI = GND to VCC 1.5 V
December 1990
2


Part Number 74HC160
Description Presettable synchronous BCD decade counter
Maker Philips
Total Page 9 Pages
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