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Philips

74HC595 Datasheet Preview

74HC595 Datasheet

8-bit serial-in/serial or parallel-out shift register

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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jun 04




Philips

74HC595 Datasheet Preview

74HC595 Datasheet

8-bit serial-in/serial or parallel-out shift register

No Preview Available !

Philips Semiconductors
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
Product specification
74HC/HCT595
FEATURES
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typ) shift out frequency
Output capability:
– parallel outputs; bus driver
– serial output; standard
ICC category: MSI.
APPLICATIONS
Serial-to-parallel data conversion
Remote control holding register.
DESCRIPTION
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The “595” is an 8-stage serial shift register with a storage
register and 3-state outputs. The shift register and storage
register have separate clocks.
Data is shifted on the positive-going transitions of the
SHCP input. The data in each register is transferred to the
storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
SYMBOL PARAMETER
CONDITIONS
TYP.
HC HCT
tPHL/tPLH
fmax
CI
CPD
propagation delay
SHCP to Q7
STCP to Qn
MR to Q7
maximum clock frequency SHCP, STCP
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1 and 2
16
17
14
100
3.5
115
21
20
19
57
3.5
130
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC 1.5 V.
UNIT
ns
ns
ns
MHz
pF
pF
1998 Jun 04
2


Part Number 74HC595
Description 8-bit serial-in/serial or parallel-out shift register
Maker Philips
Total Page 20 Pages
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