74HC7046A Datasheet | Philips Semiconductors

INTEGRATED CIRCUITS DATA SHEET For a plete data sheet, please also download: - The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications - The IC06 74HC/HCT/HCU/HCMOS Logic Package Information - The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7046A Phase-locked-loop with lock detector Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Phase-locked-loop with lock detector Features - Low power consumption - Centre frequency up to 17 MHz (typ.) at VCC = 4.5 V - Choice of two phase parators: EXCLUSIVE-OR; edge-triggered JK flip-flop; - Excellent VCO frequency linearity - VCO-inhibit control for ON/OFF keying and for low standby power consumption - Minimal frequency drift - Operation power supply voltage range: VCO section 3.0 to 6.0 V digital section 2.0 to 6.0 V - Zero voltage offset due to op-amp buffering - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT7046 are high-speed Si-gate CMOS devices and are specified in pliance with JEDEC standard no. 7. The 74HC/HCT7046 are phase-locked-loop circuits that prise a linear voltage-controlled oscillator (VCO) and two different phase parators (PC1 and PC2) with a mon signal input amplifier and a mon parator input. A lock detector is provided and this gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (GND). The value of the CLD capacitor can be determined, using information supplied in Fig.32. The input signal can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input December 1990 amplifiers. With a passive low-pass filter, the “7046” forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques. VCO The VCO...