74HC7080 Datasheet | Philips Semiconductors

FEATURES - Word-length easily expanded by cascading - Generates either even or odd parity for 16-data bits - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT7080 are high-speed Si-gate CMOS devices. They are specified in pliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT7080 The 74HC/HCT7080 are 16-bit parity generators or checkers monly used to detect errors in high-speed data transmission or data retrieval systems. The even and odd parity output is available for generating or checking even/odd parity up to 16-bits. The even/odd parity output (E/O) is HIGH when an even number of data inputs (I0 to I15) are HIGH and the cascade/even-odd-changing input (X) is HIGH. Expansion to larger word sizes is acplished by connecting the even/odd parity output (E/O) to the cascade/even-odd-changing input (X) of the final stage. TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay In to E/O X to E/O CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL ×VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 29 12 3.5 24 32 15 3.5 25 ns ns p F p F HCT UNIT December 1990 Philips Semiconductors Product specification 16-bit even/odd parity generator/checker PIN DESCRIPTION PIN NO. 1 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18 10 19 20 SYMBOL X I0 to I15 GND E/O VCC 74HC/HCT7080 NAME AND FUNCTION cascade/even-odd-changing input data inputs ground (0 V) even/odd parity output positive supply voltage Fig.1 Pin configuration. Fig.2 Logic...