74HC75 Datasheet | Philips Semiconductors

FEATURES - plementary Q and Q outputs - VCC and GND on the centre pins - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT75 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. 74HC/HCT75 The 74HC/HCT75 have four bistable latches. The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE1-2 and LE3-4). When LEn-n is HIGH, the data enters the latches and appears at the n Q outputs. The n Q outputs follow the data inputs (n D) as long as LEn-n is HIGH (transparent). The data on the n D inputs one set-up time prior to the HIGH-to-LOW transition of the LEn-n will be stored in the latches. The latched outputs remain stable as long as the LEn-n is LOW. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay n D to n Q, n Q LEn-n to n Q, n Q CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. input capacitance power dissipation capacitance per latch notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 11 11 3.5 42 12 11 3.5 42 ns ns p F p F HCT UNIT December 1990 Philips Semiconductors Product specification Quad bistable transparent latch PIN DESCRIPTION PIN NO. 1, 14, 11, 8 2, 3, 6, 7 4 5 12 13 16, 15, 10, 9 SYMBOL 1Q to 4Q 1D to 4D LE3-4 VCC GND LE1-2 1Q to 4Q NAME AND FUNCTION plementary latch outputs data inputs latch enable input, latches 3 and 4 (active HIGH) positive supply voltage ground (0 V) latch enable input, latches 1 and 2 (active HIGH) latch...