74HCT160 Datasheet | Philips Semiconductors

INTEGRATED CIRCUITS DATA SHEET For a plete data sheet, please also download: - The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications - The IC06 74HC/HCT/HCU/HCMOS Logic Package Information - The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT160 Presettable synchronous BCD decade counter; asynchronous reset Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Presettable synchronous BCD decade counter; asynchronous reset Features - Synchronous counting and loading - Two count enable inputs for n-bit cascading - Positive-edge triggered clock - Asynchronous reset - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT160 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable QUICK REFERENCE DATA GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER t PHL propagation delay CP to Qn CP to TC MR to Qn MR to TC CET to TC propagation delay CP to Qn CP to TC CET to TC maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 39 34 p F CONDITIONS HC CL = 15 p F; VCC = 5 V 19 21 21 21 14 19 21 14 61 3.5 HCT 21 24 23 26 14 21 20 7 31 3.5 ns ns ns ns ns ns ns ns MHz p F UNIT Notes 74HC/HCT160 input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place...