74HCT195
Overview
- Asynchronous master reset
- J, K, (D) inputs to the first stage
- Fully synchronous serial or parallel data transfer
- Shift right and parallel load capability
- Complement output from the last stage
- Output capability: standard
- ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT195 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT195 performs serial, parallel, serial-to-parallel or parallel-to-serial data transfer at very high speeds. The “195” operates on two primary modes: shift right (Qo→Q1) and parallel load, which are controlled QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
