4-bit parallel access shift register.
* Asynchronous master reset
* J, K, (D) inputs to the first stage
* Fully synchronous serial or parallel data transfer
* Shift right and parallel load cap.
and by tying the pins together, the simple D-type input for general applications. The “195” appears as four common clock.
The 74HC/HCT195 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT195 performs serial, parallel, serial-to-parallel or parallel-to-.
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