74LV163 Datasheet | Philips Semiconductors

FEATURES - Optimized for low voltage applications: 1.0 to 3.6 V - Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V - Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, - Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, - Synchronous counting and loading - Two count enable inputs for n-bit cascading - Positive-edge triggered clock - Synchronous reset - Output capability: standard - ICC category: MSI DESCRIPTION The 74LV163 is a low-voltage Si-gate CMOS device and is pin and function patible with 74HC/HCT163. The 74LV163 is a synchronous presettable binary counter which features an internal look-head carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops Tamb = 25°C Tamb = 25°C clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for MR are met). This action occurs regardless of the levels at PE, CET and CEP inputs. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level...