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AN189 Datasheet

Balanced Modulator / Demodulator Applications

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Philips Semiconductors
Balanced modulator/demodulator applications
using the MC1496/1596
Application note
AN189
BALANCED MODULATOR/DEMODULATOR
APPLICATIONS USING MC1496/MC1596
The MC1496 is a monolithic transistor array arranged as a balanced
modulator-demodulator. The device takes advantage of the excellent
matching qualities of monolithic devices to provide superior carrier
and signal rejection. Carrier suppressions of 50dB at 10MHz are
typical with no external balancing networks required.
Applications include AM and suppressed carrier modulators, AM
and FM demodulators, and phase detectors.
THEORY OF OPERATION
As Figure 1 suggests, the topography includes three differential
amplifiers. Internal connections are made such that the output
becomes a product of the two input signals VC and VS.
To accomplish this the differential pairs Q1-Q2 and Q3-Q4, with their
cross-coupled collectors, are driven into saturation by the zero
crossings of the carrier signal VC. With a low level signal, VS driving
the third differential amplifier Q5-Q6, the output voltage will be full
wave multiplication of VC and VS. Thus for sine wave signals, VOUT
becomes:
VOUT + EXEY ƪcos(wx ) wy)t ) cos(wx * wy)tƫ
(1)
As seen by equation (1) the output voltage will contain the sum and
difference frequencies of the two original signals. In addition, with
the carrier input ports being driven into saturation, the output will
contain the odd harmonics of the carrier signals. (See Figure 4.)
VO(+)
6
VO(–)
12
Q1 Q2
Q3 Q4
10
CARRIER(–) 8
INPUT (+)
4
(–)
SIGNAL
INPUT
1
(+)
5
BIAS
Q5
Q7
D1
Q6
2
GAIN
ADJUST
3
Q8
R1
14 500
NOTE:
V–
All resistor values are in ohms
R3
500
R2
500
Figure 1. Balanced Modulator Schematic
SR00774
Internally provided with the device are two current sources driven by
a temperature-compensated bias network. Since the transistor
geometries are the same and since VBE matching in monolithic
devices is excellent, the currents through Q7 and Q8 will be identical
to the current set at Pin 5. Figures 2 and 3 illustrate typical biasing
arrangements from split and single-ended supplies, respectively.
Of primary interest in beginning the bias circuitry design is relating
available power supplies and desired output voltages to device
requirements with a minimum of external components.
The transistors are connected in a cascode fashion. Therefore,
sufficient collector voltage must be supplied to avoid saturation if
linear operation is to be achieved. Voltages greater than 2V are
sufficient in most applications.
Biasing is achieved with simple resistor divider networks as shown
in Figure 3. This configuration assumes the presence of symmetrical
supplies. Explaining the DC biasing technique is probably best
accomplished by an example. Thus, the initial assumptions and
criteria are set forth:
1. Output swing greater than 4VP-P.
2. Positive and negative supplies of 6V are available.
3. Collector current is 2mA. It should be noted here that the collec-
tor output current is equal to the current set in the current
sources.
As a matter of convenience, the carrier signal ports are referenced
to ground. If desired, the modulation signal ports could be ground
referenced with slight changes in the bias arrangement. With the
carrier inputs at DC ground, the quiescent operating point of the
outputs should be at one-half the total positive voltage or 3V for this
case. Thus, a collector load resistor is selected which drops 3V at
2mA or 1.5k. A quick check at this point reveals that with these
loads and current levels the peak-to-peak output swing will be
greater than 4V. It remains to set the current source level and proper
biasing of the signal ports.
The voltage at Pin 5 is expressed by
VBIAS + VBE + 500 @ IS
where IS is the current set in the current sources.
VCC
R3
RS
RS
R2
RS
RS
R1
RL
GAIN
SELECT
RL
500 500 500
NOTE:
All resistor values are in ohms
Figure 2. Single-Supply Biasing
SR00775
BIASING
Since the MC1496 was intended for a multitude of different functions
as well as a myriad of supply voltages, the biasing techniques are
specified by the individual application. This allows the user complete
1988 May
1 Rev 1. 1993 Dec




Philips

AN189 Datasheet Preview

AN189 Datasheet

Balanced Modulator / Demodulator Applications

No Preview Available !

Philips Semiconductors
Balanced modulator/demodulator applications using
the MC1496/1596
Application note
AN189
freedom to choose gain, current levels, and power supplies. The
device can be operated with single-ended or dual supplies.
+6V
1.5k
1.5k
RS
RS
2.2k RS
2.2k
RS
GAIN
SELECT
500 500
500
NOTE:
All resistor values are in ohms
-6V SR00776
Figure 3. Dual Supply Biasing
VBIAS = VBE = 500 × IS
where IS is the current set in the current sources.
For the example VBE is 700mV at room temperature and the bias
voltage at Pin 5 becomes 1.7V. Because of the cascode
configuration, both the collectors of the current sources and the
collectors of the signal transistors must have some voltage to
operate properly. Hence, the remaining voltage of the negative
supply (–6V+1.7V=–4.3V) is split between these transistors by
biasing the signal transistor bases at –2.15V. Countless other bias
arrangements can be used with other power supply voltages. The
important thing to remember is that sufficient DC voltage is applied
to each bias point to avoid collector saturation over the expected
signal wings.
BALANCED MODULATOR
In the primary application of balanced modulation, generation of
double sideband suppressed carrier modulation is accomplished.
Due to the balance of both modulation and carrier inputs, the output,
as mentioned, contains the sum and difference frequencies while
attenuating the fundamentals. Upper and lower sideband signals are
the strongest signals present with harmonic sidebands being of
diminishing amplitudes as characterized by Figure 4.
Gain of the 1496 is set by including emitter degeneration resistance
located as RE in Figure 5. Degeneration also allows the maximum
signal level of the modulation to be increased. In general, linear
response defines the maximum input signal as
Vs 15 RE (Peak)
and the gain is given by
AVS
+
RE
RL
) 2re
(2)
This approximation is good for high levels of carrier signals. Table 1
summarizes the gain for different carrier signals.
As seen from Table 1, the output spectrum suffers an amplitude
increase of undesired sideband signals when either the modulation
or carrier signals are high. Indeed, the modulation level can be
increased if RE is increased without significant consequence.
However, large carrier signals cause odd harmonic sidebands
(Figure 4) to increase. At the same time, due to imperfections of the
carrier waveforms and small imbalances of the device, the second
harmonic rejection will be seriously degraded. Output filtering is
often used with high carrier levels to remove all but the desired
sideband. The filter removes unwanted signals while the high carrier
level guards against amplitude variations and maximizes gain.
Broadband modulators, without benefit of filters, are implemented
using low carrier and modulation signals to maximize linearity and
minimize spurious sidebands.
NOTES:
FREQUENCY
fC Carrier Fundamental
fS Modulating Signal
fC ± fS Fundamental Carrier Sidebands
fC ± nfS Fundamental Carrier Sideband Harmonics
nfC Carrier Harmonics
nfC ± nfS Carrier Harmonic Sidebands
Figure 4. Modulator Frequency Spectrum
1988 May
2
SR00777


Part Number AN189
Description Balanced Modulator / Demodulator Applications
Maker Philips
Total Page 5 Pages
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