Balanced modulator/demodulator applications
using the MC1496/1596
APPLICATIONS USING MC1496/MC1596
The MC1496 is a monolithic transistor array arranged as a balanced
modulator-demodulator. The device takes advantage of the excellent
matching qualities of monolithic devices to provide superior carrier
and signal rejection. Carrier suppressions of 50dB at 10MHz are
typical with no external balancing networks required.
Applications include AM and suppressed carrier modulators, AM
and FM demodulators, and phase detectors.
THEORY OF OPERATION
As Figure 1 suggests, the topography includes three differential
amplifiers. Internal connections are made such that the output
becomes a product of the two input signals VC and VS.
To accomplish this the differential pairs Q1-Q2 and Q3-Q4, with their
cross-coupled collectors, are driven into saturation by the zero
crossings of the carrier signal VC. With a low level signal, VS driving
the third differential amplifier Q5-Q6, the output voltage will be full
wave multiplication of VC and VS. Thus for sine wave signals, VOUT
VOUT + EXEY ƪcos(wx ) wy)t ) cos(wx * wy)tƫ
As seen by equation (1) the output voltage will contain the sum and
difference frequencies of the two original signals. In addition, with
the carrier input ports being driven into saturation, the output will
contain the odd harmonics of the carrier signals. (See Figure 4.)
All resistor values are in ohms
Figure 1. Balanced Modulator Schematic
Internally provided with the device are two current sources driven by
a temperature-compensated bias network. Since the transistor
geometries are the same and since VBE matching in monolithic
devices is excellent, the currents through Q7 and Q8 will be identical
to the current set at Pin 5. Figures 2 and 3 illustrate typical biasing
arrangements from split and single-ended supplies, respectively.
Of primary interest in beginning the bias circuitry design is relating
available power supplies and desired output voltages to device
requirements with a minimum of external components.
The transistors are connected in a cascode fashion. Therefore,
sufficient collector voltage must be supplied to avoid saturation if
linear operation is to be achieved. Voltages greater than 2V are
sufficient in most applications.
Biasing is achieved with simple resistor divider networks as shown
in Figure 3. This configuration assumes the presence of symmetrical
supplies. Explaining the DC biasing technique is probably best
accomplished by an example. Thus, the initial assumptions and
criteria are set forth:
1. Output swing greater than 4VP-P.
2. Positive and negative supplies of 6V are available.
3. Collector current is 2mA. It should be noted here that the collec-
tor output current is equal to the current set in the current
As a matter of convenience, the carrier signal ports are referenced
to ground. If desired, the modulation signal ports could be ground
referenced with slight changes in the bias arrangement. With the
carrier inputs at DC ground, the quiescent operating point of the
outputs should be at one-half the total positive voltage or 3V for this
case. Thus, a collector load resistor is selected which drops 3V at
2mA or 1.5kΩ. A quick check at this point reveals that with these
loads and current levels the peak-to-peak output swing will be
greater than 4V. It remains to set the current source level and proper
biasing of the signal ports.
The voltage at Pin 5 is expressed by
VBIAS + VBE + 500 @ IS
where IS is the current set in the current sources.
500 500 500
All resistor values are in ohms
Figure 2. Single-Supply Biasing
Since the MC1496 was intended for a multitude of different functions
as well as a myriad of supply voltages, the biasing techniques are
specified by the individual application. This allows the user complete
1 Rev 1. 1993 Dec