TSA5059 Datasheet | Philips Semiconductors

INTEGRATED CIRCUITS DATA SHEET TSA5059 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer Preliminary specification File under Integrated Circuits, IC02 1999 Oct 05 Philips Semiconductors Preliminary specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer Features - plete 2.7 GHz single chip system - Optimized for low phase noise - Selectable divide-by-two prescaler - Operation up to 2.7 GHz with and without divide-by-two prescaler - Selectable reference divider ratio - patible with UK-DTT (Digital Terrestrial Television) offset requirements - Selectable crystal/parison frequency output - Four selectable charge pump currents - Four selectable I2C-bus addresses - Standard and fast mode I2C-bus - I2C-bus patible with 3.3 and 5 V microcontrollers - 5-level Analog-to-Digital Converter (ADC) - Low power consumption - 33 V tuning voltage drive - Three I/O ports and one output port. APPLICATIONS - SAT, TV, VCR and cable tuning systems - Digital set-top boxes. GENERAL DESCRIPTION The TSA5059 is a single chip PLL frequency synthesizer designed for satellite and terrestrial tuning systems up to 2.7 GHz. The RF preamplifier drives the 17-bit main divider enabling a step size equal to the parison frequency, for an input frequency up to 2.7 GHz. A fixed divide-by-two additional prescaler can be inserted between the preamplifier and the main divider to give a software patibility with TSA5059 existing ICs. In this case, the step size is twice the parison frequency. The parison frequency is obtained from an on-chip crystal oscillator that can also be driven from an external source. Either the crystal frequency or the parison frequency can be switched to the XT/P output pin to drive the reference input of another synthesizer or the clock input of a digital demodulation IC. Both divided and parison frequency are pared into the fast phase detector which drives the charge pump. The loop amplifier is also...