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UJA1061 - Low speed CAN/LIN system basis chip

General Description

ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Introduction Fail-safe system controller Fail-safe mode Start-up mode Restart mode Normal mode Standby mode Sleep mode Flash mode On-chip oscillator Watchdog Watchdog start-up behaviour Watchdog window behaviour Watchdog time-out beha

Key Features

  • General System features Fail-safe features CAN physical layer LIN physical layer.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com INTEGRATED CIRCUITS DATA SHEET UJA1061 Low speed CAN/LIN system basis chip Objective specification 2004 Mar 22 Philips Semiconductors Low speed CAN/LIN system basis chip Objective specification UJA1061 CONTENTS 1 1.1 1.2 1.3 1.4 1.5 2 3 4 5 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.7 6.7.1 6.7.2 6.7.3 6.8 6.8.1 6.8.