PO74HSTL314A buffer equivalent, 3.3v 2:4 differential clock/data fanout buffer.
. Patented Technology . Four HSTL differential outputs . The two pair of LVDS/LVPECL/HSTL/ differential or single-ended inputs . Hot-swappable/-insertable . Operating fr.
The device is implemented on 0.35um CMOS technology and has a fully differential internal architecture that is optimize.
Image gallery
Download