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Power Innovations Limited

TISP83121DR Datasheet Preview

TISP83121DR Datasheet

DUAL-GATE UNIDIRECTIONAL OVERVOLTAGE PROTECTOR

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TISP83121D
DUAL-GATE UNIDIRECTIONAL OVERVOLTAGE PROTECTOR
Copyright © 1999, Power Innovations Limited, UK
FEBRUARY 1999
OVERVOLTAGE PROTECTION FOR DUAL-VOLTAGE RINGING SLICS
q Programmable Protection Configurations up
to ±100 V
D PACKAGE
(TOP VIEW)
q Typically 5 Lines Protected by Two
TISP83121D + Diode Steering Networks
q High Surge Current
- 150 A 10/1000 µs
- 150 A 10/700 µs
- 500 A 8/20 µs
q Pin compatible with the LCP3121
- Functional Replacement in Diode Steering
Network Applications
- 50% more surge current
K1
8K
G1 2
7A
G2 3
6A
K4
5K
MD6XAYA
For operation at the rated current values connect
pins 1, 4, 5 and 8 together.
device symbol
A
q Small Outline Surface Mount Package
- Available Ordering Options
G2
CARRIER
Tube
Taped and reeled
PART #
TISP83121D
TISP83121DR
description
The TISP83121D is a dual-gate reverse-blocking
unidirectional thyristor designed for the
protection of dual-voltage ringing SLICs
(Subscriber Line Interface Circuits) against
overvoltages on the telephone line caused by
lightning, a.c. power contact and induction.
The device chip is a four-layer NPNP silicon
thyristor structure which has an electrode
connection to every layer. For negative
overvoltage protection the TISP83121D is used
in a common anode configuration with the
voltage to be limited applied to the cathode (K)
terminal and the negative reference potential
applied to the gate 1 (G1) terminal. For positive
overvoltage protection the TISP83121D is used
in a common cathode configuration with the
voltage to be limited applied to the anode (A)
terminal and the positive reference potential
applied to the gate 2 (G2) terminal.
The TISP83121D is a unidirectional protector
and to prevent reverse bias, requires the use of a
series diode between the protected line
conductor and the protector. Further, the gate
reference supply voltage requires an
appropriately poled series diode to prevent the
G1
K SD6XAKA
supply from being shorted when the
TISP83121D crowbars.
Under low level power cross conditions the
TISP83121D gate current will charge the gate
reference supply. If the reference supply cannot
absorb the charging current its potential will
increase, possibly to damaging levels. To avoid
excessive voltage levels a clamp (zener or
avalanche breakdown diode) may be added in
shunt with the supply. Alternatively, a grounded
collector emitter-follower may be used to reduce
the charging current by the transistors HFE value.
This monolithic protection device is made with a
ion-implanted epitaxial-planar technology to give
a consistent protection performance and be
virtually transparent to the system in normal
operation.
PRODUCT INFORMATION
Information is current as of publication date. Products conform to specifications in accordance
with the terms of Power Innovations standard warranty. Production processing does not
necessarily include testing of all parameters.
1




Power Innovations Limited

TISP83121DR Datasheet Preview

TISP83121DR Datasheet

DUAL-GATE UNIDIRECTIONAL OVERVOLTAGE PROTECTOR

No Preview Available !

TISP83121D
DUAL-GATE UNIDIRECTIONAL OVERVOLTAGE PROTECTOR
FEBRUARY 1999
absolute maximum ratings
RATING
Repetitive peak off-state voltage, 0 °C to 70 °C
Non-repetitive peak on-state pulse current (see Notes 1 and 2)
10/1000 µs (GR-1089-CORE, open-circuit voltage wave shape 10/1000 µs)
5/310 µs (CCITT K20/21, open-circuit voltage wave shape 7 kV10/700 µs)
8/20 µs (ANSI C62.41, open-circuit voltage wave shape 1.2/50 µs)
Non-repetitive peak on-state current, 50 Hz, halfwave rectified sinewave, (see Notes 1 and 2)
100 ms
1s
900 s
Junction temperature
Storage temperature range
SYMBOL
VDRM
ITSP
ITSM
TJ
Tstg
VALUE
100
UNIT
V
150
A
150
500
22
8
3
-40 to +150
-65 to +150
A
°C
°C
NOTES: 1. Initially the protector must be in thermal equilibrium with 0 °C < TJ < 70 °C. The surge may be repeated after the device returns to
its initial conditions. For operation at the rated current value, pins 1, 4, 5 and 8 must be connected together.
2. Above 70 °C, derate linearly to zero at 150 °C lead temperature.
electrical characteristics, TJ = 25 °C (unless otherwise noted)
ID
IDRM
IH
IR
IG1T
IG2T
VG1T
VG2T
CAK
PARAMETER
TEST CONDITIONS
Off-state current
Vd = 70 V, IG = 0
Repetitive peak off-state
current
Vd = VDRM = 100 V, IG = 0, 0 °C to 70 °C
Holding current
Reverse current
Gate G1 trigger current
Gate G2 trigger current
G1-K trigger voltage
G2-A trigger voltage
Anode to cathode off-
state capacitance
IT = 1 A, di/dt = -1A/ms
VR = 0.3 V
IT = +1 A, tp(g) = 20 µs
IT = +1 A, tp(g) = 20 µs
IT = +1 A, tp(g) = 20 µs
IT = +1 A, tp(g) = 20 µs
TJ = 0 to 70 °C
TJ = 25 °C
TJ = 70 °C
f = 1 MHz, Vd = 1 VRMS, VD = 5 V, IG = 0 (see Note 3)
MIN TYP MAX UNIT
1 µA
10 µA
300
90 mA
60
1 mA
+200 mA
-180 mA
+1.8
V
-1.8 V
100 pF
NOTE 3: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured
device terminals are decoupled to the guard terminal of the bridge.
thermal characteristics
PARAMETER
RθJA Junction to free air thermal resistance
TEST CONDITIONS
TA = 25 °C, EIA/JESD51-3 PCB,
EIA/JESD51-2 environment, IT = ITSM(900)
MIN TYP MAX UNIT
105 °C/W
PRODUCT INFORMATION
2


Part Number TISP83121DR
Description DUAL-GATE UNIDIRECTIONAL OVERVOLTAGE PROTECTOR
Maker Power Innovations Limited
Total Page 7 Pages
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