HYB25D512160CF Datasheet | Qimonda

Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics. Features - - - - - - - - - - - - Burst Lengths: 2, 4, or 8 CAS Latency: 2, 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported t RAP=t RCD 7.8 µs Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 patible) I/O VDDQ = 2.5 V ± 0.2 V VDD = 2.5 V ± 0.2 V P-TFBGA-60-11 package P-TSOPII-66-1 package Ro HS pliant Products1) - Double data rate architecture: two data transfers per clock cycle - Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver - DQS is edge-aligned with data for reads and is centeraligned with data for writes - Differential clock inputs (CK and CK) - Four internal banks for concurrent operation - Data mask (DM) for write data - DLL aligns DQ and DQS transitions with CK transitions - mands entered on each positive CK edge; data and data mask referenced to both edges of DQS TABLE 1 Performance for - 5 and - 6 Part Number Speed Code Speed Grade Max. Clock Frequency ponent @CL3 @CL2.5 @CL2 - 5 DDR400B - 6 DDR333B 166 166 133 Unit - MHz MHz MHz f CK3 f CK2.5 f CK2 200 166 133 1) Ro HS pliant Product: Restriction of the use of certain hazardous substances (Ro HS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.31, 2006-09 03292006-3TFJ-HNV3 Internet Data Sheet HYB25D512[400/160/800]C[E/T/F/C](L) 512-Mbit Double-Data-Rate SDRAM Description Read...