• Part: HYB25D512160CF
  • Description: DDR SDRAM
  • Manufacturer: Qimonda
  • Size: 1.90 MB
HYB25D512160CF Datasheet (PDF) Download
Qimonda
HYB25D512160CF

Key Features

  • Burst Lengths: 2, 4, or 8 CAS Latency: 2, 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported tRAP=tRCD 7.8 µs Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 compatible) I/O VDDQ = 2.5 V ± 0.2 V VDD = 2.5 V ± 0.2 V P-TFBGA-60-11 package P-TSOPII-66-1 package RoHS Compliant Products1)
  • Double data rate architecture: two data transfers per clock cycle
  • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
  • DQS is edge-aligned with data for reads and is cent